Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33136 )
Change subject: mb/up/squared: Remove unnecessary code ......................................................................
Patch Set 6:
(9 comments)
This change is ready for review.
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c File src/mainboard/up/squared/ramstage.c:
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 32: silconfig->IpuEn = 0x0; // 0x1
set to zero by soc if ipu pci device is set to off in devicetree
Done
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 46: silconfig->IshEnable = 0x0; // 0x1
set to zero by soc if ish pci device is set to off in devicetree
Done
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 47: silconfig->SpiEiss = 0x0; // 0x1
set by soc tp zero
Done
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 49: silconfig->SdcardEnabled = 0x0; // 0x1
set to zero by soc if sdcard pci device is set to off in devicetree
Done
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 52: silconfig->VtdEnable = 0x1; // 0x0
set by soc if enable_vtd is set in devicetree
Done
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 53: silconfig->MonitorMwaitEnable = 0x0; // 0x1
set by soc code
Done
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 57: silconfig->PcieRootPortEn[0] = 0x1; // 0x0
set by soc if PCIe device in devicetree
Done
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 62: silconfig->PcieRpHotPlug[1] = 0x0; // 0x1
set by soc to register "pcie_rp_hotplug_enable" in devicetree
I would leave this here, since most of the PCIe root port options are here and thus it's less fragmented.
https://review.coreboot.org/#/c/33136/5/src/mainboard/up/squared/ramstage.c@... PS5, Line 65: silconfig->PcieRpClkReqNumber[1] = 0x3; // 0x5
set by soc if register "pcie_rp_clkreq_pin" is in devicetree
Same