Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG@8 PS1, Line 8: You should probably describe why you're pulling those values from the descriptors. Similarly, are we certain AGESA isn't doing something it shouldn't prior to the native coreboot code kicking in? And how that lines up w/ the pcie configuration?