Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76046?usp=email )
Change subject: include/amdblocks/post_code.h: Change post code prefix to POSTCODE ......................................................................
include/amdblocks/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name.
The files was changed by running the following bash script from the top level directory.
filedir=src/soc/amd/common/block/include/amdblocks/post_codes.h sed -i'' '1,${s/#define POST_/#define POSTCODE_/g;}' $filedir myArray=`grep -e "^#define POSTCODE_" $filedir | grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2` for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g" done
Change-Id: I7c0963391b2ed647048d741b087d8ee01dd7bdde Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/phoenix/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 12 files changed, 39 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/76046/1
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index b287eca..5e77263 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -57,7 +57,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */
- post_code(POST_BOOTBLOCK_PRE_C_DONE) + post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
call bootblock_c_entry
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 2bf5e23..63a6b07 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -13,7 +13,7 @@
void __noreturn romstage_main(void) { - post_code(POST_ROMSTAGE_MAIN); + post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 63342a7..2bd3f50 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -42,7 +42,7 @@ pushl %eax /* tsc[31:0] */
before_carstage: - post_code(POST_BOOTBLOCK_PRE_C_DONE) + post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index bc5f8d9..eb556fa 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -7,7 +7,7 @@
.global bootblock_resume_entry bootblock_resume_entry: - post_code(POST_BOOTBLOCK_RESUME_ENTRY) + post_code(POSTCODE_BOOTBLOCK_RESUME_ENTRY)
/* Get an early timestamp */ rdtsc @@ -57,7 +57,7 @@ pushl %eax /* tsc[31:0] */ #endif
- post_code(POST_BOOTBLOCK_PRE_C_DONE) + post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h index dbd546f..10056e7 100644 --- a/src/soc/amd/common/block/include/amdblocks/post_codes.h +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -3,31 +3,31 @@ #ifndef AMD_BLOCK_POST_CODES_H #define AMD_BLOCK_POST_CODES_H
-#define POST_AGESA_AMDINITRESET 0x37 -#define POST_AGESA_AMDINITEARLY 0x38 +#define POSTCODE_AGESA_AMDINITRESET 0x37 +#define POSTCODE_AGESA_AMDINITEARLY 0x38
-#define POST_ROMSTAGE_MAIN 0x40 +#define POSTCODE_ROMSTAGE_MAIN 0x40
-#define POST_AGESA_AMDINITPOST 0x40 -#define POST_AGESA_AMDINITPOST_DONE 0x41 +#define POSTCODE_AGESA_AMDINITPOST 0x40 +#define POSTCODE_AGESA_AMDINITPOST_DONE 0x41
-#define POST_PSP_NOTIFY_DRAM 0x42 -#define POST_PSP_NOTIFY_DRAM_DONE 0x43 +#define POSTCODE_PSP_NOTIFY_DRAM 0x42 +#define POSTCODE_PSP_NOTIFY_DRAM_DONE 0x43
-#define POST_ROMSTAGE_RUN_POSTCAR 0x44 +#define POSTCODE_ROMSTAGE_RUN_POSTCAR 0x44
-#define POST_PSP_LOAD_SMU 0x46 -#define POST_AGESA_AMDINITENV 0x47 -#define POST_AGESA_AMDS3LATERESTORE 0x48 +#define POSTCODE_PSP_LOAD_SMU 0x46 +#define POSTCODE_AGESA_AMDINITENV 0x47 +#define POSTCODE_AGESA_AMDS3LATERESTORE 0x48
-#define POST_AGESA_AMDINITRESUME 0x60 -#define POST_AGESA_AMDINITRESUME_DONE 0x61 +#define POSTCODE_AGESA_AMDINITRESUME 0x60 +#define POSTCODE_AGESA_AMDINITRESUME_DONE 0x61
-#define POST_BOOTBLOCK_SOC_EARLY_INIT 0x90 +#define POSTCODE_BOOTBLOCK_SOC_EARLY_INIT 0x90
-#define POST_BOOTBLOCK_RESUME_ENTRY 0xb0 -#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY 0xa0 -#define POST_BOOTBLOCK_PRE_C_DONE 0xa2 +#define POSTCODE_BOOTBLOCK_RESUME_ENTRY 0xb0 +#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY 0xa0 +#define POSTCODE_BOOTBLOCK_PRE_C_DONE 0xa2
#endif diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c index 2bf5e23..63a6b07 100644 --- a/src/soc/amd/glinda/romstage.c +++ b/src/soc/amd/glinda/romstage.c @@ -13,7 +13,7 @@
void __noreturn romstage_main(void) { - post_code(POST_ROMSTAGE_MAIN); + post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c index 046c351..83a8bf9 100644 --- a/src/soc/amd/mendocino/romstage.c +++ b/src/soc/amd/mendocino/romstage.c @@ -14,7 +14,7 @@
void __noreturn romstage_main(void) { - post_code(POST_ROMSTAGE_MAIN); + post_code(POSTCODE_ROMSTAGE_MAIN);
if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) write_stb_to_console(); diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c index 2bf5e23..63a6b07 100644 --- a/src/soc/amd/phoenix/romstage.c +++ b/src/soc/amd/phoenix/romstage.c @@ -13,7 +13,7 @@
void __noreturn romstage_main(void) { - post_code(POST_ROMSTAGE_MAIN); + post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 846460d..c43b249 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -14,7 +14,7 @@
void __noreturn romstage_main(void) { - post_code(POST_ROMSTAGE_MAIN); + post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call. */ fill_chipset_state(); diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 1d41477..a1ddb5c 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -77,7 +77,7 @@ void bootblock_soc_early_init(void) { bootblock_fch_early_init(); - post_code(POST_BOOTBLOCK_SOC_EARLY_INIT); + post_code(POSTCODE_BOOTBLOCK_SOC_EARLY_INIT); }
void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 60bc921..eaa0e9a 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -108,15 +108,15 @@ static void earliest_ramstage(void *unused) { if (!acpi_is_wakeup_s3()) { - post_code(POST_PSP_LOAD_SMU); + post_code(POSTCODE_PSP_LOAD_SMU); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
- post_code(POST_AGESA_AMDINITENV); + post_code(POSTCODE_AGESA_AMDINITENV); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ - post_code(POST_AGESA_AMDS3LATERESTORE); + post_code(POSTCODE_AGESA_AMDS3LATERESTORE); do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 460218e..fc918f9 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -37,10 +37,10 @@
static void agesa_call(void) { - post_code(POST_AGESA_AMDINITRESET); + post_code(POSTCODE_AGESA_AMDINITRESET); do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
- post_code(POST_AGESA_AMDINITEARLY); + post_code(POSTCODE_AGESA_AMDINITEARLY); /* APs will not exit amdinitearly */ do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } @@ -68,10 +68,10 @@ bsp_agesa_call();
if (!s3_resume) { - post_code(POST_AGESA_AMDINITPOST); + post_code(POSTCODE_AGESA_AMDINITPOST); do_agesawrapper(AMD_INIT_POST, "amdinitpost");
- post_code(POST_AGESA_AMDINITPOST_DONE); + post_code(POSTCODE_AGESA_AMDINITPOST_DONE); /* * TODO: This is a hack to work around current AGESA behavior. * AGESA needs to change to reflect that coreboot owns @@ -101,16 +101,16 @@ wrmsr(SYSCFG_MSR, sys_cfg); } else { printk(BIOS_INFO, "S3 detected\n"); - post_code(POST_AGESA_AMDINITRESUME); + post_code(POSTCODE_AGESA_AMDINITRESUME); do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
- post_code(POST_AGESA_AMDINITRESUME_DONE); + post_code(POSTCODE_AGESA_AMDINITRESUME_DONE); }
- post_code(POST_PSP_NOTIFY_DRAM); + post_code(POSTCODE_PSP_NOTIFY_DRAM); psp_notify_dram();
- post_code(POST_PSP_NOTIFY_DRAM_DONE); + post_code(POSTCODE_PSP_NOTIFY_DRAM_DONE); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) @@ -119,7 +119,7 @@ if (CONFIG(SMM_TSEG)) smm_list_regions();
- post_code(POST_ROMSTAGE_RUN_POSTCAR); + post_code(POSTCODE_ROMSTAGE_RUN_POSTCAR); prepare_and_run_postcar(); }