[coreboot-gerrit] [S] Change in coreboot[master]: mb/siemens/mc_ehl1: Disable L1 prefetcher

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68668 )

Change subject: mb/siemens/mc_ehl1: Disable L1 prefetcher
......................................................................

mb/siemens/mc_ehl1: Disable L1 prefetcher

The highly real time driven application executed on mc_ehl1 has shown
that the L1 prefetcher on Elkhart Lake is too aggressive which in the
end leads to an increased number of cache misses. Disabling the L1
prefetcher boosts up the performance (in some cases by more than 10 %)
in this specific use case.

Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/68668/1

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 44a1c38..1c11008 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -132,6 +132,9 @@
    	.vcc_low_high_us = 50,
    }"

+	# Disable L1 prefetcher
+	register "L1_prefetcher_disable" = "true"
+

device domain 0 on
    	device pci 00.0 on	end # Host Bridge