[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/cmn/block/cse: Support sending EOP from payload

[Kapil Porwal (Code Review)]

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74765 )

Change subject: soc/intel/cmn/block/cse: Support sending EOP from payload
......................................................................

soc/intel/cmn/block/cse: Support sending EOP from payload

Add support for sending EOP from payload

BUG=b:279184514
TEST=Verify sending EOP from depthcharge

Signed-off-by: Kapil Porwal 
Change-Id: I0fbb9fd0f8522eefad39960ca3167c2ba764f523
---
M src/include/boot/coreboot_tables.h
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_eop.c
4 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/74765/1

diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index e209e4b..5d33cd7 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -47,4 +47,6 @@
 /* Add VBOOT VBNV offsets. */
 void lb_table_add_vbnv_cmos(struct lb_header *header);

+void lb_cse_send_eop_and_finalize(void);
+
 #endif /* COREBOOT_TABLES_H */
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 73cb51bc..80b8c25 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -107,6 +107,16 @@
      request is posted (at CSE .final device operation) and the
      time coreboot check for its completion (BS_PAYLOAD_LOAD).

+config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_CSE
+	depends on !SOC_INTEL_CSE_SEND_EOP_LATE
+	depends on !SOC_INTEL_CSE_SEND_EOP_EARLY
+	depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC
+	help
+	  Use this config to send End Of Post (EOP) using payload. Coreboot supplies a function
+	  pointer to send EOP to payload via SYSINFO table.
+
 config SOC_INTEL_CSE_LITE_SKU
    bool
    default n
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 1aa3454..8deef01 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1408,6 +1408,7 @@
 void cse_late_finalize(void)
 {
    if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) &&
+	    !CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) &&
        !CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC))
    	return;

@@ -1434,6 +1435,7 @@
     * will be run once the EOP command has successfully been completed.
     */
    if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) ||
+	    CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) ||
        CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC))
    	return;

diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index dd67e59..264f3c4 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
+#include <boot/coreboot_tables.h>
 #include <bootstate.h>
 #include <console/console.h>
 #include <intelblocks/cse.h>
@@ -301,10 +302,22 @@
    	do_send_end_of_post(true);

if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) ||
+	    CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) ||
        CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC))
    	cse_late_finalize();
 }

+void lb_cse_send_eop_and_finalize(void)
+{
+	if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD))
+		return;
+
+	printk(BIOS_INFO, "Sending End-of-POST from the payload!\n");
+
+	send_cse_eop_with_late_finalize(NULL);
+}
+
+#if !CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD)
 /*
  * Ideally, to give coreboot maximum flexibility, sending EOP would be done as
  * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must
@@ -319,3 +332,4 @@
 #else
 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, send_cse_eop_with_late_finalize, NULL);
 #endif
+#endif