Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51174 )
Change subject: soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K ......................................................................
soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K
Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size to 128K. With this change, more DRAM calibration logs can be kept in CBMEM console.
BUG=none TEST=emerge-asurada coreboot TEST=Hayato boots BRANCH=none
Change-Id: I896884d298e197149f75865e9d00579124a34404 Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/soc/mediatek/mt8192/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51174/1
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 2624d82..db8ae46 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -26,7 +26,6 @@ TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) - PRERAM_CBMEM_CONSOLE(0x00104004, 15K - 4) CBFS_MCACHE(0x00107c00, 8K) TIMESTAMP(0x00109c00, 1K) STACK(0x0010a000, 12K) @@ -49,6 +48,7 @@ */ DRAM_INIT_CODE(0x00250000, 256K) PRERAM_CBFS_CACHE(0x00290000, 48K) + PRERAM_CBMEM_CONSOLE(0x002d0000, 128K) SRAM_L2C_END(0x00300000)
DRAM_START(0x40000000)