[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 89:

(1 comment)

File src/soc/intel/pantherlake/acpi.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/5a137350_2164acaf?usp... :
PS37, Line 30: 	C_STATE_C0,		/* 0 */
             : 	C_STATE_C1,		/* 1 */
             : 	C_STATE_C1E,		/* 2 */
             : 	C_STATE_C6_SHORT_LAT,	/* 3 */
             : 	C_STATE_C6_LONG_LAT,	/* 4 */
             : 	C_STATE_C7_SHORT_LAT,	/* 5 */
             : 	C_STATE_C7_LONG_LAT,	/* 6 */
             : 	C_STATE_C7S_SHORT_LAT,	/* 7 */
             : 	C_STATE_C7S_LONG_LAT,	/* 8 */
             : 	C_STATE_C8,		/* 9 */
             : 	C_STATE_C9,		/* 10 */
             : 	C_STATE_C10,		/* 11 */
             : 	NUM_C_STATES
> > I will come back with the data, checking Internally with c states owner. […]

Hi, I will be back on this info. Checking internally with the owners.