[coreboot-gerrit] Change in coreboot[master]: mb/emulation/qemu-q35: Solve lint-001 error

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49930 )

Change subject: mb/emulation/qemu-q35: Solve lint-001 error
......................................................................

mb/emulation/qemu-q35: Solve lint-001 error

lint-001-no-global-config-in-romstage error on
D0F0_PCIEXBAR_LO.

DOF0_PCIEXBAR_LO is defined in bootblock.c and
romstage.c.
Place D0F0_PCIEXBAR_XX in local gm35.h.

BUG = N/A
TEST = Build and boot QEMU x86 q35/ich9

Change-Id: Ia5ac9eb797de996186282193647313b9f7b42624
Signed-off-by: Frans Hendriks 
---
M src/mainboard/emulation/qemu-q35/bootblock.c
A src/mainboard/emulation/qemu-q35/gm35.h
M src/mainboard/emulation/qemu-q35/romstage.c
3 files changed, 11 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/49930/1

diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index efb3a4f..6de3dd8 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -6,9 +6,7 @@
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <console/console.h>

-/* Just define these here, there is no gm35.h file to include. */
-#define D0F0_PCIEXBAR_LO 0x60
-#define D0F0_PCIEXBAR_HI 0x64
+#include "gm35.h"

static void bootblock_northbridge_init(void)
 {
diff --git a/src/mainboard/emulation/qemu-q35/gm35.h b/src/mainboard/emulation/qemu-q35/gm35.h
new file mode 100644
index 0000000..62b04b8
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/gm35.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_EMU_GM35_H__
+#define __MAINBOARD_EMU_GM35_H__
+
+#define D0F0_PCIEXBAR_LO 0x60
+#define D0F0_PCIEXBAR_HI 0x64
+
+#endif
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index 504c655..92b6113 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -6,7 +6,7 @@
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <device/pci_ops.h>

-#define D0F0_PCIEXBAR_LO 0x60
+#include "gm35.h"

static void mainboard_machine_check(void)
 {