Attention is currently required from: Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56617
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Clear RTC_BATTERY_DEAD ......................................................................
soc/intel/alderlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty and RTC_BATTERY_DEAD is set), if coreboot persistently requests recovery before FSP-M finishes (which clears RTC_BATTERY_DEAD towards the end of its execution), then vbnv_cmos_failed() will still return 1. Therefore, immediately after reading (and returning 1 if set) RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc).
BUG=b:181678769
Change-Id: I9dc21c19ea8ce561e9655e189ec26aba7a07967e Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/alderlake/pmutil.c 1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56617/2