Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25600
Change subject: nb/intel/i945: Use parallel MP init ......................................................................
nb/intel/i945: Use parallel MP init
untested
Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/Makefile.inc M src/cpu/intel/model_f4x/model_f4x_init.c M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/northbridge.c 10 files changed, 20 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/25600/1
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 0703099..eec544d 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -2,5 +2,6 @@ subdirs-y += ../../x86/name subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index dd7bbc8..5ea39a9 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -86,15 +86,18 @@ x86_enable_cache();
/* Update the microcode */ - intel_update_microcode_from_cbfs(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_update_microcode_from_cbfs();
/* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { + x86_setup_mtrrs(); + x86_mtrr_check(); + }
/* Enable the local CPU APICs */ setup_lapic(); @@ -111,7 +114,8 @@ /* TODO: PIC thermal sensor control */
/* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 13e08f0..46ae7c7 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -2,5 +2,6 @@ subdirs-y += ../../x86/name subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-y += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 96830c4..a6daf17 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -119,17 +119,10 @@ /* Turn on caching if we haven't already */ x86_enable_cache();
- /* Update the microcode */ - intel_update_microcode_from_cbfs(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); - /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
@@ -147,9 +140,6 @@
/* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my CPU siblings */ - intel_sibling_init(cpu); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 7367914..19b2e93 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_f3x_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index d853a63..4b8168e 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -27,7 +27,7 @@ /* Turn on caching if we haven't already */ x86_enable_cache();
- if (!intel_ht_sibling()) { + if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -40,7 +40,8 @@ setup_lapic();
/* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 2f11d7f..6fbc9ae 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_f4x_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 9eb5115..c15cc97 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -27,7 +27,7 @@ /* Turn on caching if we haven't already */ x86_enable_cache();
- if (!intel_ht_sibling()) { + if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -40,7 +40,8 @@ setup_lapic();
/* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); };
static struct device_operations cpu_dev_ops = { diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index dcf3fb5..05e2d49 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -29,6 +29,7 @@ select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select SMM_TSEG + select PARALLEL_MP
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 94f7dac..7c1d540 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -136,26 +136,6 @@ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram); }
-/* - * Really doesn't belong here but will go away with parallel mp init, - * so let it be here for a while... - */ -int cpu_get_apic_id_map(int *apic_id_map) -{ - unsigned int i; - - /* Logical processors (threads) per core */ - const struct cpuid_result cpuid1 = cpuid(1); - /* Read number of cores. */ - const char cores = (cpuid1.ebx >> 16) & 0xf; - - /* TODO in parallel MP cpuid(1).ebx */ - for (i = 0; i < cores; i++) - apic_id_map[i] = i; - - return cores; -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. @@ -221,7 +201,7 @@
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); }
static struct device_operations cpu_bus_ops = {