Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56584 )
Change subject: mb/google/brya/variants/primus: Update NVMe clk ......................................................................
mb/google/brya/variants/primus: Update NVMe clk
According to the schematic diagram of proto, modify the clock of nvme from the baseboard default to src0.
BUG=b:194487277
Signed-off-by: Malik_Hsu malik_hsu@wistron.corp-partner.google.com Change-Id: I41be517b434513bca2332ec37e54f56910302bb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/primus/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Malik Hsu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 6464b8b..39aa77e 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -176,6 +176,14 @@ device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE9-12 SSD device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682""