ChiaLing has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email )
Change subject: mb/google/dedede: Support variant specific power limits ......................................................................
mb/google/dedede: Support variant specific power limits
With newer dedede design, it's required to config corresponding psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kind of adapter.
BUG=b:281479111 TEST=emerge-dedede coreboot and check correct register value on DUT
Signed-off-by: Chia-Ling Hou chia-ling.hou@intel.com Change-Id: I583c930379233322c41027805369f81d02000ee7 --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dedede/variants/baseboard/ramstage.c 2 files changed, 211 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75680/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index edb2b07..cc262f9 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -48,6 +48,53 @@ /* Modify devictree settings during ramstage. */ void variant_devtree_update(void);
+struct cpu_power_limits { + uint16_t mchid; + u8 cpu_tdp; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; + unsigned int pl4_power; +}; + +struct system_power_limits { + uint16_t mchid; + u8 cpu_tdp; + /* PsysPL1 in Watts */ + unsigned int psys_pl1_power; + /* PsysPL2 in Watts */ + unsigned int psys_pl2_power; +}; + +struct psys_config { + /* + * The efficiency of type-c chargers + * For example, 'efficiency = 97' means setting 97% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ + unsigned int efficiency; + + /* The maximum current maps to the Psys signal */ + unsigned int psys_imax_ma; + + /* The voltage of barrel jack */ + unsigned int bj_volts_mv; +}; + +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(const struct cpu_power_limits *limits, + size_t num_entries); + +/* + * Modify Power Limit and PsysPL devictree settings during ramstage. + * Note, this function must be called in front of calling variant_update_power_limits. + */ +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config); + /* Modify LTE devictree settings during ramstage. */ void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio);
diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c new file mode 100644 index 0000000..51dbddc --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <gpio.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <device/pci_ops.h> +#include <intelblocks/power_limit.h> +#include <chip.h> +#include <drivers/intel/dptf/chip.h> +#include <soc/pci_devs.h> + +#define LTE_USB_PORT_ID 3 +#define LTE_USB_PORT_TYPE 2 + +#define SET_PSYSPL2(e, w) ((e) * (w) / 100) + +static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries, + size_t *intel_idx, size_t *dedede_idx) +{ + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + size_t i = 0; + + for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) { + if (mchid == cpuid_to_jsl[i].pci_did && tdp == cpuid_to_jsl[i].cpu_tdp) { + *intel_idx = cpuid_to_jsl[i].limits; + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_jsl)) { + printk(BIOS_ERR, "Cannot find correct intel sku index.\n"); + return false; + } + + for (i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + *dedede_idx = i; + break; + } + } + + if (i == num_entries) { + printk(BIOS_ERR, "Cannot find correct dedede sku index.\n"); + return false; + } + + return true; +} + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + size_t intel_idx, dedede_idx; + struct drivers_intel_dptf_config *config; + struct dptf_power_limits *settings; + config_t *conf; + struct soc_power_limits_config *soc_config; + + if (!num_entries) + return; + + const struct device *dev = pcidev_path_on_root(SA_DEVFN_DPTF); + if(!dev || !dev->chip_info) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &dedede_idx)) + return; + + config = dev->chip_info; + settings = &config->controls.power_limits; + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + settings->pl1.min_power = limits[dedede_idx].pl1_min_power; + settings->pl1.max_power = limits[dedede_idx].pl1_max_power; + settings->pl2.min_power = limits[dedede_idx].pl2_min_power; + settings->pl2.max_power = limits[dedede_idx].pl2_max_power; + + if (soc_config->tdp_pl2_override != 0) { + settings->pl2.max_power = soc_config->tdp_pl2_override * 1000; + settings->pl2.min_power = settings->pl2.max_power; + } + + if (soc_config->tdp_pl4 == 0) + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[dedede_idx].pl4_power, + MILLIWATTS_TO_WATTS); + + printk(BIOS_INFO, "Overriding power limits PL1(mW) (%u, %u) PL2(mW) (%u, %u) PL4 (%u)\n", + settings->pl1.min_power, + settings->pl1.max_power, + settings->pl2.min_power, + settings->pl2.max_power, + soc_config->tdp_pl4); +} + +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config_psys) +{ + struct soc_power_limits_config *soc_config; + size_t intel_idx, dedede_idx; + u16 volts_mv, current_ma; + enum usb_chg_type type; + u32 psyspl2, pl2; + u32 pl2_default; + config_t *conf; + u32 watts; + int rv; + + if (!num_entries) + return; + + const struct device *dev = pcidev_path_on_root(SA_DEVFN_DPTF); + if(!dev || !dev->chip_info) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &dedede_idx)) + return; + + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + soc_config->tdp_pl4 = 0; + + pl2_default = DIV_ROUND_UP(limits[dedede_idx].pl2_max_power, MILLIWATTS_TO_WATTS); + rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + + /* set psyspl2 to 97% of adapter rating */ + psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts); + + /* Limit PL2 if the adapter is with lower capability */ + pl2 = (psyspl2 > pl2_default) ? pl2_default : psyspl2; + + } else { + /* Input type is barrel jack */ + volts_mv = config_psys->bj_volts_mv; + psyspl2 = sys_limits[dedede_idx].psys_pl2_power; + pl2 = pl2_default; + } + + /* voltage unit is milliVolts and current is in milliAmps */ + soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); + conf->PsysPmax = soc_config->psys_pmax; + + soc_config->tdp_psyspl1 = sys_limits[dedede_idx].psys_pl1_power; + soc_config->tdp_pl2_override = pl2; + soc_config->tdp_psyspl2 = psyspl2; + soc_config->tdp_pl4 = psyspl2 - soc_config->min_rop; + + printk(BIOS_INFO, "Overriding PL2 (%u) PL4 (%u) PsysPL1 (%u) PsysPL2 (%u) Psys_Pmax (%u)\n", + soc_config->tdp_pl2_override, + soc_config->tdp_pl4, + soc_config->tdp_psyspl1, + soc_config->tdp_psyspl2, + soc_config->psys_pmax); +}