Attention is currently required from: Martin L Roth, Michał Żygowski, Paul Menzel, Subrata Banik, Tarun Tuli.
Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68987?usp=email )
Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash ......................................................................
Patch Set 8: Code-Review+1
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68987/comment/75587457_69d91dbf : PS3, Line 13: This change allows to : keep PCIe 5.0 functioning even if CSME/HECI is not functional.
Changed to PCIe 5. […]
Done
Patchset:
PS8: One typo caught by Jenkins left.
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/68987/comment/a648bc57_61bd9da9 : PS7, Line 532: Set this option to avoid communication with ME to fetch the PCIe 5.0 : HSPHY firmware on each boot
Rephrased
Done
File src/soc/intel/alderlake/hsphy.c:
https://review.coreboot.org/c/coreboot/+/68987/comment/f6688501_74b1fd9f : PS3, Line 233: if (hsphy_cache_valid(hsphy_fw_cache)) {
I have changed the flow to try HECI command so we can fetch the newest HSPHY FW and cache it if need […]
Done
https://review.coreboot.org/c/coreboot/+/68987/comment/128e959b_22256349 : PS3, Line 234: printk(BIOS_INFO, "HSPHY: HSPHY cache valid, skipping update\n");
Indeed, Krystian also pointed it out. […]
Done
File src/soc/intel/alderlake/hsphy.c:
https://review.coreboot.org/c/coreboot/+/68987/comment/7f403d59_0f0803d2 : PS7, Line 378: printk(BIOS_ERR, "Failed to load HSPHY FW from cache\n");
Fixed
Done
https://review.coreboot.org/c/coreboot/+/68987/comment/a05546aa_febb84ab : PS7, Line 391: printk(BIOS_ERR, "%s: CSME not enabled or not visible, but required\n",
Fixed
Done
https://review.coreboot.org/c/coreboot/+/68987/comment/43cef9b8_cd60ed8e : PS7, Line 400: printk(BIOS_ERR, "Failed to load HSPHY FW from cache\n");
Fixed
Done