Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62739 )
Change subject: mb/google/brya: set GPP_D0 to GPO ......................................................................
mb/google/brya: set GPP_D0 to GPO
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP firmware successfully.
BUG=b:222188263, b:223906569 TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint Firmware Test.
Signed-off-by: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Reviewed-by: YH Lin yueherngl@google.com Reviewed-by: Subrata Banik subratabanik@google.com --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index b8d1761..da0048a 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -118,7 +118,7 @@ PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE),
/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */