Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44429 )
Change subject: util: Add spd_tools to generate DDR4 SPDs for TGL boards ......................................................................
Patch Set 19:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44429/19/util/spd_tools/intel/ddr4/... File util/spd_tools/intel/ddr4/gen_spd.go:
https://review.coreboot.org/c/coreboot/+/44429/19/util/spd_tools/intel/ddr4/... PS19, Line 1133: func getCASLatencies(memAttribs *memAttributes) string { I suggest adding a validator to check if the override casLatencies matches the default casLatencies so we don't accumulate unnecessary overrides.
https://review.coreboot.org/c/coreboot/+/44429/19/util/spd_tools/intel/ddr4/... PS19, Line 1149: "9 10 11 12 13 14 15 16 17 18 19 20", nit: adding a comment with the index or speed bin would be helpful here.