Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42736 )
Change subject: soc/amd: refactor I2c gpio code to use gpio_get_address ......................................................................
soc/amd: refactor I2c gpio code to use gpio_get_address
Change-Id: I29cf27acfa119339796d485611ee8db288482b0f --- M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/stoneyridge/i2c.c M src/soc/amd/stoneyridge/include/soc/i2c.h 4 files changed, 29 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42736/1
diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 6f34573..751dbb0 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -179,6 +179,13 @@ const struct soc_amd_picasso_config *cfg; struct soc_amd_i2c_save save_table[saved_pins_count]; uint8_t i, j, control; + /* I2C0-1 is not accessible from the x86. */ + uint32_t *i2c_gpio_ptr[I2C_MASTER_DEV_COUNT] = { + NULL, + NULL, + (uint32_t *)gpio_get_address(I2C2_SCL_PIN), + (uint32_t *)gpio_get_address(I2C3_SCL_PIN), + };
cfg = config_of_soc(); control = cfg->i2c_scl_reset & GPIO_I2C_MASK; @@ -196,19 +203,19 @@ */ for (j = 0; j < 9; j++) { if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[2], GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[3], GPIO_SCL_LOW);
- read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[2], GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[3], GPIO_SCL_HIGH);
- read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); }
diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 58c27a4..4b63712 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -17,8 +17,6 @@ #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19
-#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) -#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) #define GPIO_SCL_HIGH 0 #define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE
diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 8667d92..ec1ecc5 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -163,6 +163,12 @@ const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct soc_amd_i2c_save save_table[saved_pins_count]; uint8_t i, j, control; + void *i2c_gpio_ptr[I2C_DEVICE_COUNT] = { + (void *)gpio_get_address(I2C0_SCL_PIN), + (void *)gpio_get_address(I2C1_SCL_PIN), + (void *)gpio_get_address(I2C2_SCL_PIN), + (void *)gpio_get_address(I2C3_SCL_PIN), + };
if (!dev || !dev->chip_info) return; @@ -182,27 +188,27 @@ */ for (j = 0; j < 9; j++) { if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[0], GPIO_SCL_LOW); if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[1], GPIO_SCL_LOW); if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[2], GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[3], GPIO_SCL_LOW);
- read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[0], GPIO_SCL_HIGH); if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[1], GPIO_SCL_HIGH); if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[2], GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[3], GPIO_SCL_HIGH);
- read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); }
diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 874f7d1..844ff1b 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -21,11 +21,6 @@ #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19
-#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) -#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) -#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) -#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) - #define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx #define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx