[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60179 )

Change subject: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function
......................................................................

soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function

The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak 
Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d
---
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/tigerlake/pcie_rp.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/60179/1

diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index ff10c51..f5ed892 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -121,4 +121,7 @@
 struct device; /* Not necessary to include all of device/device.h */
 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev);

+/* Return the virtual wire index that represents CPU-side PCIe root ports */
+int soc_get_cpu_rp_vw_idx(const struct device *dev);
+
 #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */
diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c
index a9a6c7f..b543d9a 100644
--- a/src/soc/intel/tigerlake/pcie_rp.c
+++ b/src/soc/intel/tigerlake/pcie_rp.c
@@ -49,3 +49,22 @@

return PCIE_RP_UNKNOWN;
 }
+
+int soc_get_cpu_rp_vw_idx(const struct device *dev)
+{
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return -1;
+
+	switch (dev->path.pci.devfn) {
+	case SA_DEVFN_PEG1:
+		return CPU_CPIE_VW_IDX_BASE + 2;
+	case SA_DEVFN_PEG2:
+		return CPU_CPIE_VW_IDX_BASE + 1;
+	case SA_DEVFN_PEG1:
+		return CPU_CPIE_VW_IDX_BASE;
+	case SA_DEVFN_CPU_PCIE:
+		return CPU_CPIE_VW_IDX_BASE + 3;
+	default:
+		return -1;
+	}
+}