Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5450
-gerrit
commit 85e714612899b4ac16e53750e8299e7a99d8db38 Author: Felix Held felix-coreboot@felixheld.de Date: Wed Jun 4 23:15:26 2014 +0200
superio/nuvoton: Add support for Nuvoton NCT6776
Add support for both NCT6776D and NCT6776F devices.
Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c Signed-off-by: Felix Held felix-coreboot@felixheld.de --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6776/Makefile.inc | 22 +++++++++ src/superio/nuvoton/nct6776/nct6776.h | 62 ++++++++++++++++++++++++ src/superio/nuvoton/nct6776/superio.c | 82 ++++++++++++++++++++++++++++++++ 5 files changed, 171 insertions(+)
diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 350c8dd..8c70520 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -28,3 +28,7 @@ config SUPERIO_NUVOTON_WPCM450 config SUPERIO_NUVOTON_NCT5104D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6776 + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 1ce6963..57ce02f 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -22,3 +22,4 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c
subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 diff --git a/src/superio/nuvoton/nct6776/Makefile.inc b/src/superio/nuvoton/nct6776/Makefile.inc new file mode 100755 index 0000000..45bd755 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held felix-coreboot@felixheld.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h new file mode 100755 index 0000000..f6f31ef --- /dev/null +++ b/src/superio/nuvoton/nct6776/nct6776.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held felix-coreboot@felixheld.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +#ifndef SUPERIO_NUVOTON_NCT6776_H +#define SUPERIO_NUVOTON_NCT6776_H + +/* Logical Device Numbers (LDN). */ +#define NCT6776_FDC 0x00 /* Floppy */ +#define NCT6776_PP 0x01 /* Parallel port */ +#define NCT6776_SP1 0x02 /* Com1 */ +#define NCT6776_SP2 0x03 /* Com2 & IR */ +#define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6776_CIR 0x06 +#define NCT6776_GPIO6789_V 0x07 +#define NCT6776_WDT1_GPIO01A_V 0x08 +#define NCT6776_GPIO1234567_V 0x09 +#define NCT6776_ACPI 0x0A +#define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT6776_VID 0x0D +#define NCT6776_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT6776_SVID 0x14 +#define NCT6776_DSLP 0x16 /* Deep sleep */ +#define NCT6776_GPIOA_LDN 0x17 + +/* virtual LDN for GPIO and WDT */ +#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V) + +#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //? + +#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V) +#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V) + +#endif /* SUPERIO_NUVOTON_NCT6776_H */ diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c new file mode 100755 index 0000000..6712750 --- /dev/null +++ b/src/superio/nuvoton/nct6776/superio.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held felix-coreboot@felixheld.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> +#include "nct6776.h" + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +static void nct6776_init(device_t dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6776_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + //TODO: set field from struct io_info seems to be unused. why set this to 0 or 4? + { &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_ACPI}, + { &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6776_VID}, + { &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO_PP_OD}, + { &ops, NCT6776_SVID}, + { &ops, NCT6776_DSLP}, + { &ops, NCT6776_GPIOA_LDN}, + { &ops, NCT6776_WDT1}, + { &ops, NCT6776_GPIOBASE, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO0}, + { &ops, NCT6776_GPIO1}, + { &ops, NCT6776_GPIO2}, + { &ops, NCT6776_GPIO3}, + { &ops, NCT6776_GPIO4}, + { &ops, NCT6776_GPIO5}, + { &ops, NCT6776_GPIO6}, + { &ops, NCT6776_GPIO7}, + { &ops, NCT6776_GPIO8}, + { &ops, NCT6776_GPIO9}, + { &ops, NCT6776_GPIOA}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6776_ops = { + CHIP_NAME("NUVOTON NCT6776 Super I/O") + .enable_dev = enable_dev, +};