Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41690 )
Change subject: mb/ocp/deltalake: Config PCH PCIe ports in devicetree ......................................................................
Patch Set 17:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41690/16/src/mainboard/ocp/deltalak... File src/mainboard/ocp/deltalake/romstage.c:
https://review.coreboot.org/c/coreboot/+/41690/16/src/mainboard/ocp/deltalak... PS16, Line 84:
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https://review.coreboot.org/c/coreboot/+/41690/16/src/mainboard/ocp/deltalak... PS16, Line 86:
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Done
https://review.coreboot.org/c/coreboot/+/41690/17/src/vendorcode/intel/fsp/f... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/41690/17/src/vendorcode/intel/fsp/f... PS17, Line 49: #define MAX_PCH_PCIE_PORT 20 see comment below
https://review.coreboot.org/c/coreboot/+/41690/17/src/vendorcode/intel/fsp/f... PS17, Line 145: /** : UPD_PCH_PCIE_PORT: : ForceEnable - Enable/Disable PCH PCIe port : PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set : **/ : struct UPD_PCH_PCIE_PORT { : UINT8 ForceEnable; : UINT8 PortLinkSpeed; : }; : : /** : PCIe Link Speed Selection : **/ : typedef enum { : PcieAuto = 0, : PcieGen1, : PcieGen2, : PcieGen3 : } PCIE_LINK_SPEED; Any reason to add this structure and enum to FspmUpd.h? if are not, this should be moved to src/soc/intel/xeon_sp/cpx/chip.h