[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings.

[Stanley Wu (Code Review)]

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48150 )

Change subject: mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings.
......................................................................

mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings.

Update lindar gpio settings for Synaptics trackpad no function issue.
Update I2C5 bus freq to 400kHz.

BUG=b:160013582
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device. Verify trackpad function workable.

Signed-off-by: Stanley Wu 
Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf
---
M src/mainboard/google/volteer/variants/lindar/gpio.c
M src/mainboard/google/volteer/variants/lindar/overridetree.cb
2 files changed, 41 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/48150/1

diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c
index 4f3d5f7..f99ffbd 100644
--- a/src/mainboard/google/volteer/variants/lindar/gpio.c
+++ b/src/mainboard/google/volteer/variants/lindar/gpio.c
@@ -134,6 +134,9 @@
    /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),

+	/* E15 : ISH_GP6 ==> NC */
+	PAD_NC(GPP_E15, NONE),
+
    /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
    PAD_CFG_GPO(GPP_H11, 1, DEEP),
 };
diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
index 2e61071..7bdb625 100644
--- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
@@ -9,6 +9,44 @@
    register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0

register "SaGv" = "SaGv_Disabled"
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | Touchscreen               |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 0,
+			.fall_time_ns = 0,
+			.data_hold_time_ns = 0,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 163,
+				.scl_hcnt = 75,
+				.sda_hold = 36,
+			},
+		},
+	}"
    # I2C Port Config
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci,