Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34809 )
Change subject: arch/x86: Add postcar_frame_common_mtrrs() ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34809/2/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/34809/2/src/arch/x86/postcar_loader... PS2, Line 125: /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
CACHE_TMP_RAMTOP is fairly arbitrary. […]
Well currently we do. The only case I remember is some SIPI for MP_INIT that has to be within first megabyte? I would not mind changing this to that with followup.
https://review.coreboot.org/c/coreboot/+/34809/2/src/cpu/intel/car/romstage.... File src/cpu/intel/car/romstage.c:
https://review.coreboot.org/c/coreboot/+/34809/2/src/cpu/intel/car/romstage.... PS2, Line 36: if (!pcf->skip_common_mtrr)
I don't think we should be making these decisions here. […]
Ack