[coreboot-gerrit] Change in coreboot[master]: address of riscv register is incorrect

[Anonymous Coward (Code Review)]

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20047

Change subject: address of riscv register is incorrect
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address of riscv register is incorrect

I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.

Change-Id: Ib80faa5d9836fe13f964829928e9f07ca5cd3dbd
Signed-off-by: wxjstz 
---
M src/arch/riscv/virtual_memory.c
1 file changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/20047/1

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 2c440d2..abb8b30 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -316,6 +316,5 @@
    // Until we trust our toolchain use the hardcoded constants.
    // These were in flux and people who get the older toolchain
    // will have difficult-to-debug failures.
-	write_csr(/*mucounteren*/0x320, 7);
-	write_csr(/*mscounteren*/0x321, 7);
+	write_csr(/*mucounteren*/0x306, 7);
 }