[coreboot-gerrit] Change in coreboot[master]: nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache`

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45921 )

Change subject: nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache`
......................................................................

nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache`

With SMM_TSEG_SIZE being fixed at 8 MiB, the code caches 8 MiB below
TSEG and the TSEG region itself. Make the latter more obvious.

Change-Id: I7ac7db0237f4b948eba06f728a16e3760708c016
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/ironlake/memmap.c
1 file changed, 4 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45921/1

diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c
index 221ae92..4ec8e3a 100644
--- a/src/northbridge/intel/ironlake/memmap.c
+++ b/src/northbridge/intel/ironlake/memmap.c
@@ -37,11 +37,10 @@
 {
    uintptr_t top_of_ram;

-	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
-	 * above top of the ram. This satisfies MTRR alignment requirement
-	 * with different TSEG size configurations.
-	 */
+	/* Cache 8 MiB below the top of RAM */
    top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
    postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
-	postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
+
+	/* Cache TSEG region */
+	postcar_enable_tseg_cache(pcf);
 }