Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42308 )
Change subject: mb/google/volteer: Enable HECI interface ......................................................................
mb/google/volteer: Enable HECI interface
This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite.
BUG=b:159615125 TEST=Build and boot volteer. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0
Change-Id: I68eb51c6a0af77982c060767993265764a2bc926 Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42308 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Jamie Ryu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 705da1d..0c581a5 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -43,6 +43,9 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
+ # Enable heci communication + register "HeciEnabled" = "1" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "0"