[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Nico Huber, Furquan Shaikh, Paul Menzel, Meera Ravindranath, Subrata Banik, Nick Vaccaro, Ronak Kanabar, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 )

Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
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Patch Set 8:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/52730/comment/b23e10ec_2075be85 
PS8, Line 15: #define DDR5_CHANNELS			CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
> It seems this is the only place where DDR5_PHYSICAL_CH_WIDTH is used? […]

I see your point, Nico. EDS vol. 1 does seem to indicates it is always effectively 128 bits wide

8 channels of x16 for lpddr4x and lpddr5x or you can also convert sub-channels into wider x32 and x64, but it's still 128 wide
2 channels of x64 for ddr4
4 channels of x32 for ddr5
are the configurations that I see