[coreboot-gerrit] Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table

[Jianjun Wang (Code Review)]

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Paul Menzel, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu.
Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot_tables: Add PCIe info to coreboot table
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Patch Set 19:

(1 comment)

Patchset:

PS9:
> coreboot table entry formats should generally not be changed after they have been introduced (althou […]

According to the PCI spec, a PCI bus may have up to 32 devices, and each device may have 8 functions in maxmium, the total size of configuration space for each bus will be 32 * 8 * 4K = 1024K, so I guess the reason why Qualcomm set the mmio_size to 1MB is to mapping the whole bus (but MediaTek only mapping the minimum space each time). Anyway, I think this should be a constant value, I don't know why Qualcomm need to pass it to libpayload.

@Shelley, do you have any suggestions? Could you help to clarify these questions?

Thanks.