Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43660 )
Change subject: vc/amd/fsp/picasso: add logical to lane number in port descriptor struct ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43660/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43660/4//COMMIT_MSG@11 PS4, Line 11: fsp_pcie_descriptor struct.
The documentation in that ticket matches what I'd expect for Picasso/Dali; have to verify the mapping of the m.2 lanes that partially support both SATA and PCIe. Were the zork devices also tested with a SATA m.2 SSD or only with PCIe ones?
For Pollock the logical lane numbers match with what I'd expect, since it's an RV2 die; the mapping to the physical/GPP lane numbers is however different than I had expected. I probably don't have that much more information on Pollock than you have access to.