Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31839
Change subject: Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI ......................................................................
Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI
Some new feature added into FSP specification to perform dispatching of external PPI service from boot firmware (coreboot) to FSP.
Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M Documentation/soc/intel/fsp/index.md A Documentation/soc/intel/fsp/ppi/ppi.md 2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31839/1
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 039a389..d7f44c6 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -11,3 +11,7 @@ * [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-speci...)
* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-speci...) + +## Additional Features in FSP 2.1 specification + +- [PPI](ppi/ppi.md) diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md new file mode 100644 index 0000000..66dbf07 --- /dev/null +++ b/Documentation/soc/intel/fsp/ppi/ppi.md @@ -0,0 +1,9 @@ +# PEIM to PEIM Interface (PPI) + +This section is intended to document the purpose of creating PPI service +inside coreboot space to perform some specific operation related to CPU, +chipset using Intel FSP. This feature is added into FSP specification 2.1 +where FSP should be able to locate PPI, published by boot firmware and +able to execute the same in FSP's context. + +* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference-guide...)