[coreboot-gerrit] [XS] Change in coreboot[master]: Add SPR_MEM_CAPACITY macro

[Ziang Wang (Code Review)]

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75759?usp=email )

Change subject: Add SPR_MEM_CAPACITY macro
......................................................................

Add SPR_MEM_CAPACITY macro

Change-Id: Idabcafa29f18dac5c0d50a2fca0bcd19f441d34c
Signed-off-by: Ziang Wang 
---
M src/soc/intel/xeon_sp/spr/romstage.c
1 file changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/75759/1

diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 62b6212..96499fc 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -22,6 +22,10 @@

#include "chip.h"

+#ifndef SPR_MEM_CAPACITY_IN_MB
+#define SPR_MEM_CAPACITY_IN_MB (6 * (1 << 20))
+#endif
+
 /* Initialize to all zero first */
 static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[MAX_SOCKET];
 static UINT8 deemphasis_list[MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET];
@@ -276,7 +280,7 @@
     * Max Capacity: (x8 256 GB 16 Gb 3DS DDR5) and (x8 512 GB Intel® Optane™
     * Persistent Memory 300 Series mapped as memory) per Socket
     */
-	mem_info->max_capacity_mib = 6 * MiB * CONFIG_MAX_SOCKET;
+	mem_info->max_capacity_mib = SPR_MEM_CAPACITY_IN_MB * CONFIG_MAX_SOCKET;
    mem_info->number_of_devices = CONFIG_DIMM_MAX;
    mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled);
    dimm_max = ARRAY_SIZE(mem_info->dimm);