Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9519
-gerrit
commit 20e1aa523d857872df01fd689dd47587374e31dd Author: Jimmy Zhang jimmzhang@nvidia.com Date: Mon Nov 3 17:38:29 2014 -0800
tegra132: Pass panel spec to lib_sysinfo
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel.
Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet.
BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode.
Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang jimmzhang@nvidia.com Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh furquan@google.com --- src/mainboard/google/rush_ryu/Kconfig | 1 + src/soc/nvidia/tegra132/Makefile.inc | 12 ++++++------ src/soc/nvidia/tegra132/display.c | 32 ++++++++++++++++++++++++++++++-- src/soc/nvidia/tegra132/soc.c | 2 ++ 4 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index da517da..ac694a7 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_I2C select EC_GOOGLE_CHROMEEC_I2C_PROTO3 select EC_SOFTWARE_SYNC + select MAINBOARD_DO_NATIVE_VGA_INIT select SPI_FLASH select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index a7485fa..82ac11a7 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -66,12 +66,12 @@ ramstage-y += cbmem.c ramstage-y += cpu.c ramstage-y += cpu_lib.S ramstage-y += clock.c -ramstage-y += display.c -ramstage-y += tegra_dsi.c -ramstage-y += mipi_dsi.c -ramstage-y += mipi.c -ramstage-y += mipi-phy.c -ramstage-y += ./jdi_25x18_display/panel-jdi-lpm102a188a.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += tegra_dsi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi_dsi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi-phy.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c
ramstage-y += soc.c ramstage-y += spi.c diff --git a/src/soc/nvidia/tegra132/display.c b/src/soc/nvidia/tegra132/display.c index 62cea02..1708b5a 100644 --- a/src/soc/nvidia/tegra132/display.c +++ b/src/soc/nvidia/tegra132/display.c @@ -29,6 +29,7 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <cbmem.h> +#include <edid.h> #include <soc/clock.h> #include <soc/nvidia/tegra/dc.h> #include <soc/funitcfg.h> @@ -289,9 +290,36 @@ void display_startup(device_t dev) return; }
- /* set up window */ + /* Set up window */ update_window(config); - printk(BIOS_INFO, "%s: display init done.\n", __func__); + + /* + * Pass panel information to cb tables + */ + struct edid edid; + /* Align bytes_per_line to 64 bytes as required by dc */ + edid.bytes_per_line = ALIGN_UP((config->xres * + config->framebuffer_bits_per_pixel / 8), 64); + edid.x_resolution = edid.bytes_per_line / + (config->framebuffer_bits_per_pixel / 8); + edid.y_resolution = config->yres; + edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + + printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " + " x_res x y_res: %d x %d, size: %d\n", + __func__, edid.bytes_per_line, + edid.framebuffer_bits_per_pixel, + edid.x_resolution, edid.y_resolution, + (edid.bytes_per_line * edid.y_resolution)); + + set_vbe_mode_info_valid(&edid, 0); + + /* + * After this point, it is payload's responsibility to allocate + * framebuffer and sets the base address to dc's + * WINBUF_START_ADDR register and enables window by setting dc's + * DISP_DISP_WIN_OPTIONS register. + */ }
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index d80a388..b91260e 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -86,10 +86,12 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops);
+#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) if (vboot_skip_display_init()) printk(BIOS_INFO, "Skipping display init.\n"); else display_startup(dev); +#endif }
static struct device_operations soc_ops = {