Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59954 )
Change subject: [WIP]: mb/google/brya: Disable autonomus GPIO PM ......................................................................
[WIP]: mb/google/brya: Disable autonomus GPIO PM
Change-Id: I6da66d8e62928d4cfff7ef2fc3a2e0ab5761bc78 Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59954/1
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 3822a2c..c5ec598 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -35,6 +35,18 @@ end
chip soc/intel/alderlake + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + + register "SaGv" = "SaGv_Enabled"
register "PsysPmax" = "145"