Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17699
-gerrit
commit 45db7402380cb8ab8464291f1bfe52be10252d55 Author: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Date: Fri Dec 2 18:14:19 2016 +0530
soc/intel/apollolake: Set PL2 in RAPL register
This patch sets the package power limit (PL2) value in RAPL register.
BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value.
Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- src/soc/intel/apollolake/chip.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ef5908c..89a2888 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -243,6 +243,10 @@ static void set_power_limits(void) limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
+ /* Set short term power limit PL2 to 15W */ + limit.hi = 0xf00 & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Program package power limits in RAPL MSR */ wrmsr(MSR_PKG_POWER_LIMIT, limit); printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, @@ -255,6 +259,7 @@ static void set_power_limits(void) * PL2 (limit.hi) is invalid for small cores */ write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); + write32(rapl_mmio_reg + 1, limit.hi); }
static void soc_init(void *data)