Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69223 )
Change subject: drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer ......................................................................
drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer
Now the CPU topology is filled in struct device during mp_init.
Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/69223 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 3 files changed, 21 insertions(+), 82 deletions(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved
diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index d286ee3..a891ba0 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -28,9 +28,6 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { - int apicid; - uint8_t package, core, thread; - if (processor_number >= MIN(get_cpu_count(), CONFIG_MAX_CPUS)) return FSP_NOT_FOUND;
@@ -39,14 +36,10 @@ if (!info) return FSP_DEVICE_ERROR;
+ struct device *dev = info->cpu; + if (processor_info_buffer == NULL) return FSP_INVALID_PARAMETER; - apicid = info->cpu->path.apic.apic_id; - - if (apicid < 0) - return FSP_DEVICE_ERROR; - - processor_info_buffer->ProcessorId = apicid;
processor_info_buffer->StatusFlag = PROCESSOR_HEALTH_STATUS_BIT | PROCESSOR_ENABLED_BIT; @@ -54,12 +47,10 @@ if (processor_number == BSP_CPU_SLOT) processor_info_buffer->StatusFlag |= PROCESSOR_AS_BSP_BIT;
- /* Fill EFI_CPU_PHYSICAL_LOCATION structure information */ - get_cpu_topology_from_apicid(apicid, &package, &core, &thread); - - processor_info_buffer->Location.Package = package; - processor_info_buffer->Location.Core = core; - processor_info_buffer->Location.Thread = thread; + processor_info_buffer->ProcessorId = dev->path.apic.apic_id; + processor_info_buffer->Location.Package = dev->path.apic.package_id; + processor_info_buffer->Location.Core = dev->path.apic.core_id; + processor_info_buffer->Location.Thread = dev->path.apic.thread_id;
return FSP_SUCCESS; } diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 3f0ee67..c317e05 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -15,23 +15,6 @@ #include <soc/soc_chip.h> #include <types.h>
-#define CPUID_EXTENDED_CPU_TOPOLOGY 0x0b -#define LEVEL_TYPE_CORE 2 -#define LEVEL_TYPE_SMT 1 - -#define CPUID_CPU_TOPOLOGY(x, val) \ - (((val) >> CPUID_CPU_TOPOLOGY_##x##_SHIFT) & CPUID_CPU_TOPOLOGY_##x##_MASK) - -#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_SHIFT 0x8 -#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_MASK 0xff -#define CPUID_CPU_TOPOLOGY_LEVEL(res) CPUID_CPU_TOPOLOGY(LEVEL_TYPE, (res).ecx) - -#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_SHIFT 0x0 -#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_MASK 0x1f -#define CPUID_CPU_TOPOLOGY_THREAD_BITS(res) CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax) -#define CPUID_CPU_TOPOLOGY_CORE_BITS(res, threadbits) \ - ((CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax)) - threadbits) - #define CPUID_PROCESSOR_FREQUENCY 0X16 #define CPUID_HYBRID_INFORMATION 0x1a
@@ -481,52 +464,6 @@ return valid_size; }
-/* Get number of bits for core ID and SMT ID */ -static void get_cpu_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - struct cpuid_result cpuid_regs; - int level_num, cpu_id_op = 0; - const uint32_t cpuid_max_func = cpuid_get_max_func(); - - /* Assert if extended CPU topology not supported */ - assert(cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY); - - cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY; - - *core_bits = level_num = 0; - cpuid_regs = cpuid_ext(cpu_id_op, level_num); - - /* Sub-leaf index 0 enumerates SMT level, if not assert */ - assert(CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) == LEVEL_TYPE_SMT); - - *thread_bits = CPUID_CPU_TOPOLOGY_THREAD_BITS(cpuid_regs); - do { - level_num++; - cpuid_regs = cpuid_ext(cpu_id_op, level_num); - if (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) == LEVEL_TYPE_CORE) { - *core_bits = CPUID_CPU_TOPOLOGY_CORE_BITS(cpuid_regs, *thread_bits); - break; - } - /* Stop when level type is invalid i.e 0 */ - } while (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs)); -} - -void get_cpu_topology_from_apicid(uint32_t apicid, uint8_t *package, - uint8_t *core, uint8_t *thread) -{ - - uint32_t core_bits, thread_bits; - - get_cpu_core_thread_bits(&core_bits, &thread_bits); - - if (package) - *package = apicid >> (thread_bits + core_bits); - if (core) - *core = (apicid >> thread_bits) & ((1 << core_bits) - 1); - if (thread) - *thread = apicid & ((1 << thread_bits) - 1); -} - static void sync_core_prmrr(void) { static msr_t msr_base, msr_mask; diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 38c43d8..cbc9e44 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -183,10 +183,6 @@ */ void enable_pm_timer_emulation(void);
-/* Derive core, package and thread information from lapic ID */ -void get_cpu_topology_from_apicid(uint32_t apicid, uint8_t *package, - uint8_t *core, uint8_t *thread); - /* * Initialize core PRMRR *