Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32175 )
Change subject: soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/32175/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32175/1//COMMIT_MSG@14 PS1, Line 14: Verified the GPIO MISCFG is getting set as per updated map.
Does GPE_STS get set correctly in DWx register? Does wake work fine each of the DWx register configu […]
I checked for GPE_STS for touchpad on hatch , verified STS set for A21(DW0) and D21(DW2) wake instances. TPM does not timeout waiting on IRQ in verstage and depthcharge(mapped to DW1). This is all on hatch.
https://review.coreboot.org/#/c/32175/1/src/soc/intel/cannonlake/include/soc... File src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/#/c/32175/1/src/soc/intel/cannonlake/include/soc... PS1, Line 25: 0
Since you are changing these, can you please add 0x in front of all the values to ensure they are co […]
Done. Updated in PS#2
https://review.coreboot.org/#/c/32175/1/src/soc/intel/cannonlake/include/soc... PS1, Line 39: #define GROUP_HVMOS 0xF
No 0x9?
It is mapped to VGPIO , since VGPIO has 40 pins, 32 is mapped to 0x8 and rest are mapped to 0x9