[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/tigerlake: Fix setting `HyperThreading`

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69534 )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/tigerlake: Fix setting `HyperThreading`
......................................................................

soc/intel/tigerlake: Fix setting `HyperThreading`

The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.

Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes 
Reviewed-by: Nico Huber 
Reviewed-by: Felix Singer 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 22 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  Felix Singer: Looks good to me, approved
  Sean Rhodes: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 6e15d50..c34892a 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -432,9 +432,6 @@
     */
    uint8_t cpu_ratio_override;

-	/* HyperThreadingDisable : Yes (1) / No (0) */
-	uint8_t HyperThreadingDisable;
-
    /*
     * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
     * Default 0. Setting this to 1 disables the DMI Power Optimizer.
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 399cb87..d4e694e 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -125,9 +125,6 @@
    m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2);
    m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3);

-	/* Hyper Threading */
-	m_cfg->HyperThreading = !config->HyperThreadingDisable;
-
    /* Disable Lock PCU Thermal Management registers */
    m_cfg->LockPTMregs = 0;
    /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */