Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50426 )
Change subject: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled`
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Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Werner, do you have an OS that would do something unwanted? The OS always has […]
In our systems we disable speed step in coreboot all the time. This is done in order to avoid CPU frequency switching in a realtime environment. And since modern kernels are able to handle all this "fancy" features and most likely enable things like this per default we chose the strategy do define the feature set in this regard in firmware. So regardless of the logic here (either enable or disable per default): in the end we will make sure for the Siemens mainboards that EIST is disabled. And since this is an option in devicetree we can do that easily.
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