[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8

[Hualin Wei (Code Review)]

Attention is currently required from: Karthik Ramasubramanian, Subrata Banik.

Hualin Wei has posted comments on this change by Hualin Wei. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email )

Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
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Patch Set 3:

(1 comment)

File src/mainboard/google/dedede/variants/awasuki/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/84951/comment/1160f349_ca9c76c5?usp... :
PS3, Line 3: PcieRpLtrEnable
> This field does not exist in soc_intel_jasperlake_config. […]

We made modifications based on CL84866,  and CL84866 defined this field.
CL84866:https://review.coreboot.org/c/coreboot/+/84866