Marc Jones (marc@marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18437
-gerrit
commit 62d5dfd2bbdf6045618a957500a2ca10eecea48c Author: Marshall Dawson marshalldawson3rd@gmail.com Date: Tue Jan 17 11:57:31 2017 -0500
cpu/amd/pi: Split CAR setup for use in multiple stages
This patch uses hints from commit e6af4be to make CAR setup more standalone. These changes will facilitate establishing CAR outside of romstage in an upcoming separate verstage patch.
Move CAR teardown to its own file that will always be in romstage, but isn't required in an earlier stage.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-by: Marc Jones marcj303@gmail.com (cherry picked from commit c648d2a0f88ac1161f5d2002f7b947cb8e56b03f)
Change-Id: I9fe53ca1fd6b1edd4d5e072849f3962c8bc95df0 Signed-off-by: Marc Jones marcj303@gmail.com --- src/cpu/amd/pi/after_raminit.S | 49 +++++++++++++++++++++++++++++++++++++++++ src/cpu/amd/pi/cache_as_ram.inc | 33 +++++---------------------- 2 files changed, 54 insertions(+), 28 deletions(-)
diff --git a/src/cpu/amd/pi/after_raminit.S b/src/cpu/amd/pi/after_raminit.S new file mode 100644 index 0000000..79cf59b --- /dev/null +++ b/src/cpu/amd/pi/after_raminit.S @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/cache.h> + +/* + * This is the common entry point after DRAM has been initialized. + */ +.global disable_cache_as_ram +disable_cache_as_ram: + /* Save return stack */ + movd 0(%esp), %xmm1 + movd %esp, %xmm0 + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + xorl %eax, %eax + + /* Restore the return stack */ + wbinvd + movd %xmm0, %esp + movd %xmm1, (%esp) + ret + +cache_as_ram_setup_out: +#ifdef __x86_64__ +.code64 +#endif diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index 24db600..0915c23 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -33,7 +33,7 @@ */
.code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out +.globl cache_as_ram_setup
cache_as_ram_setup:
@@ -136,31 +136,8 @@ cache_as_ram_setup: stop: jmp stop
-disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - AMD_DISABLE_STACK - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - xorl %eax, %eax - - /* Restore the return stack */ - wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret - -cache_as_ram_setup_out: -#ifdef __x86_64__ -.code64 +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after RAM init. */ +#if !ENV_VERSTAGE +#include "after_raminit.S" #endif