[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIE in FSP

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
PS3, Line 208: 0
> Yes, that's correct.  it's tide to 0.6.0 device and TGLU and TGLY only have 1 port(1x4).

Right, so it would be good to add that 0:6.0 device in `soc/pci_devs.h` and then do:

dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
 m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;