Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6554
-gerrit
commit 6609fe81eac919fb427ac1913e2cf8036b7d31c6 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sat Aug 9 20:22:22 2014 +1000
southbridge/amd/cs5536: Make cs5536_enable_smbus() a weak symbol
On some boards the SMBus is hardwired and so we need to override cs5536_enable_smbus() with a dummy function in the board support. Thus we make cs5536_enable_smbus() a weak symbol.
Change-Id: Iada97edf0591556b64eb8b63752379fdf0366ece Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/southbridge/amd/cs5536/cs5536.h | 6 ++++++ src/southbridge/amd/cs5536/early_setup.c | 1 + src/southbridge/amd/cs5536/early_smbus.c | 4 +--- 5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 204f0bd..080553b 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX1.C has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) { } +void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 18453ac..07bf77e 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX.2D has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) { } +void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/early_setup.c"
diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index c193d9d..faceec4 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -451,4 +451,10 @@ void chipsetinit(void); #endif #endif
+/** + * Note: Some boards do not have SMBus and are hard-wired, so we leave this + * symbol weak as to be able to override it in 'romstage.c' of board support. + */ +void cs5536_enable_smbus(void) __attribute__((weak)); + #endif /* _CS5536_H */ diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index e6ef8ad..d9a042a 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -22,6 +22,7 @@ * This file implements the initialization sequence documented in section 4.2 of * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide. */ +#include "cs5536.h"
/** * @brief Setup PCI IDSEL for CS5536 diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c index d1483b1..853f837 100644 --- a/src/southbridge/amd/cs5536/early_smbus.c +++ b/src/southbridge/amd/cs5536/early_smbus.c @@ -21,16 +21,14 @@ #include "smbus.h"
/* initialization for SMBus Controller */ -static void cs5536_enable_smbus(void) +void cs5536_enable_smbus(void) { - /* Set SCL freq and enable SMB controller */ /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */ outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);
/* Setup SMBus host controller address to 0xEF */ outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD); - }
static inline int smbus_read_byte(unsigned device, unsigned address)