Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83112?usp=email )
Change subject: soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiB ......................................................................
soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiB
This change updates the Northbridge ASL to conditionally include a QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS` is above 4 GiB.
If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the PCH reserved range, the existing handling of `SM01` remains unchanged (as a DWordMemory resource).
TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB, verified ASL output.
Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b Signed-off-by: Subrata Banik subratabanik@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112 Reviewed-by: Cliff Huang cliff.huang@intel.com Reviewed-by: Hannah Williams hannah.williams@intel.com Reviewed-by: Kapil Porwal kapilporwal@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 14 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Hannah Williams: Looks good to me, but someone else must approve Cliff Huang: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 03295b4..51b0e23 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -166,7 +166,12 @@ 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02)
-#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ +#if (CONFIG_PCR_BASE_ADDRESS >= (4ULL * GiB)) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x000000000, 0x00000000, 0x00000000, + 0x00000000,,, SM01) +#elif !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) /* SBREG BAR if outside of PCH reserved resource */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, @@ -202,13 +207,19 @@ PMIN = _SB.PCI0.MCHC.TLUD & (0xfff << 20) PLEN = PMAX - PMIN + 1
-#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ +#if (CONFIG_PCR_BASE_ADDRESS >= (4ULL * GiB)) + CreateQwordField (MCRS, SM01._MIN, SMIN) + CreateQwordField (MCRS, SM01._MAX, SMAX) + CreateQwordField (MCRS, SM01._LEN, SLEN) + SMIN = P2SB_BAR + SLEN = P2SB_SIZE + SMAX = SMIN + SLEN - 1 +#elif !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) /* Fix up SBREG BAR memory region if outside PCH reserved resource */ CreateDwordField (MCRS, SM01._MIN, SMIN) CreateDwordField (MCRS, SM01._MAX, SMAX) CreateDwordField (MCRS, SM01._LEN, SLEN) - SMIN = P2SB_BAR SLEN = P2SB_SIZE SMAX = SMIN + SLEN - 1