Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85127?usp=email )
(
20 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add PMIC MT6363 driver ......................................................................
soc/mediatek/mt8196: Add PMIC MT6363 driver
1. Add MT6363 driver in SoC folder 2. Add vtref18 set/get api 3. Add MT6363 LDO/BUCK enable api 4. Add pmif_arb for MT6363
TEST=build pass BUG=b:317009620
Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e Signed-off-by: Hope Wang hope.wang@mediatek.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85127 Reviewed-by: Yidi Lin yidilin@google.com Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/soc/mediatek/common/include/soc/mt6363.h A src/soc/mediatek/common/mt6363.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6363.c 4 files changed, 782 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/common/include/soc/mt6363.h b/src/soc/mediatek/common/include/soc/mt6363.h new file mode 100644 index 0000000..7e4487f --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mt6363.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6363_H__ +#define __SOC_MEDIATEK_MT6363_H__ + +#include <soc/spmi.h> +#include <types.h> + +enum { + PMIC_HWCID = 0x0008, + PMIC_SWCID0 = 0x000A, + PMIC_SWCID1 = 0x000B, + PMIC_TOP_CKPDN_CON0 = 0x010C, + PMIC_TOP_CKHWEN_CON0 = 0x012A, + PMIC_TOP_RST_MISC1 = 0x0139, + PMIC_TOP_RST_MISC1_SET = 0x013A, + PMIC_TOP_RST_MISC1_CLR = 0x013B, + PMIC_TOP_VRCTL_DBG_CON0 = 0x0231, + PMIC_VRCTL_VOSEL_VBUCK2 = 0x024E, + PMIC_OTP_CON0 = 0x038A, + PMIC_OTP_CON8 = 0x039A, + PMIC_OTP_CON11 = 0x03A0, + PMIC_OTP_CON12 = 0x03A2, + PMIC_OTP_CON13 = 0x03A4, + PMIC_PWRHOLD = 0x0A08, + PMIC_VCORE_DBG0 = 0x1526, + PMIC_VCORE_ELR0 = 0x152C, + PMIC_VBUCK2_DBG0 = 0x1596, + PMIC_VGPU11_DBG0 = 0x15A6, + PMIC_VBUCK4_DBG0 = 0x1696, + PMIC_VBUCK5_OP_EN_2 = 0x170F, + PMIC_VBUCK5_DBG0 = 0x1716, + PMIC_VS2_VOTER = 0x18AA, + PMIC_VS2_VOTER_CFG = 0x18B0, + PMIC_VS2_ELR0 = 0x18B4, + PMIC_VPA_CON0 = 0x1908, + PMIC_VPA_CON1 = 0x190E, + PMIC_VPA_DBG0 = 0x1914, + PMIC_BUCK_VPA_DLC_CON0 = 0x1918, + PMIC_BUCK_VPA_DLC_CON1 = 0x191A, + PMIC_VSRAM_PROC1_ELR = 0x1B44, + PMIC_VSRAM_PROC2_ELR = 0x1B46, + PMIC_LDO_VCN15_CON0 = 0x1B87, + PMIC_LDO_VRF09_CON0 = 0x1B95, + PMIC_LDO_VRF12_CON0 = 0x1Ba3, + PMIC_LDO_VRF13_CON0 = 0x1BB1, + PMIC_LDO_VRF18_CON0 = 0x1BBF, + PMIC_LDO_VTREF18_CON0 = 0x1C07, + PMIC_VSIM1_CON0 = 0x1CD0, + PMIC_LDO_VSRAM_DIGRF_CON0 = 0x1D1D, + PMIC_LDO_VSRAM_MDFE_CON0 = 0x1D87, + PMIC_VM18_CON0 = 0x1D88, + PMIC_VSRAM_PROC1_VOSEL1 = 0x1E90, + PMIC_VSRAM_PROC2_VOSEL1 = 0x1EB0, + PMIC_VTREF18_ANA_CON0 = 0x1F08, + PMIC_VTREF18_ANA_CON1 = 0x1F09, + PMIC_VM18_ANA_CON0 = 0x1F1F, + PMIC_VM18_ANA_CON1 = 0x1F20, + PMIC_VSIM1_ANA_CON0 = 0x1FA2, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; +}; + +struct pmic_efuse { + unsigned short efuse_bit; + unsigned short addr; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6363_VBUCK1 = 0, + MT6363_VBUCK2, + MT6363_VBUCK3, + MT6363_VBUCK4, + MT6363_VM18 = 7, + MT6363_MAX, +}; + +#define EFUSE_WAIT_US 5000 +#define EFUSE_BUSY 1 + +#define EFUSE_RG_VPA_OC_FT 78 + +void mt6363_init(void); +void mt6363_buck_set_voltage(u32 buck_id, u32 buck_uv); +u32 mt6363_buck_get_voltage(u32 buck_id); +void mt6363_set_vm18_voltage(u32 vm18_uv); +u32 mt6363_get_vm18_voltage(void); +void mt6363_set_vtref18_voltage(u32 vtref18_uv); +u32 mt6363_get_vtref18_voltage(void); +void mt6363_set_vsim1_voltage(u32 vsim1_uv); +u32 mt6363_get_vsim1_voltage(void); +void mt6363_enable_vpa(bool enable); +void mt6363_enable_vsim1(bool enable); +void mt6363_enable_vm18(bool enable); +void mt6363_enable_vtref18(bool enable); +void mt6363_enable_buck5(bool enable); +void mt6363_enable_vcn15(bool enable); +void mt6363_enable_vrf09(bool enable); +void mt6363_enable_vrf12(bool enable); +void mt6363_enable_vrf13(bool enable); +void mt6363_enable_vrf18(bool enable); +void mt6363_enable_vram_digrf(bool enable); +void mt6363_enable_vram_mdfe(bool enable); +void mt6363_init_pmif_arb(void); +u32 mt6363_read16(u32 reg); +void mt6363_write8(u32 reg, u8 reg_val); +void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift); +void pmic_init_setting(void); + +#endif /* __SOC_MEDIATEK_MT6363_H__ */ diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c new file mode 100644 index 0000000..9619d44 --- /dev/null +++ b/src/soc/mediatek/common/mt6363.c @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6363.h> +#include <soc/pmif.h> +#include <timer.h> + +#define MT6363_SET_DELAY_US 200 + +static const struct pmic_setting key_protect_setting[] = { + {0x39E, 0x9C, 0xFF}, + {0x39F, 0x9C, 0xFF}, + {0xFAB, 0x63, 0xFF}, + {0xFAC, 0x63, 0xFF}, + {0x142A, 0x43, 0xFF}, + {0x142B, 0x55, 0xFF}, + {0x3A7, 0x9C, 0xFF}, + {0x3A8, 0x9C, 0xFF}, + {0xA33, 0x29, 0xFF}, + {0xA34, 0x47, 0xFF}, + {0xC42, 0x06, 0xFF}, + {0xC43, 0x17, 0xFF}, +}; + +static struct pmif *pmif_arb; +u32 mt6363_read16(u32 reg) +{ + u16 rdata = 0; + + assert(pmif_arb); + pmif_arb->read16(pmif_arb, SPMI_SLAVE_4, reg, &rdata); + return rdata; +} + +void mt6363_write8(u32 reg, u8 data) +{ + assert(pmif_arb); + pmif_arb->write(pmif_arb, SPMI_SLAVE_4, reg, data); +} + +static void mt6363_write16(u32 reg, u16 data) +{ + assert(pmif_arb); + pmif_arb->write16(pmif_arb, SPMI_SLAVE_4, reg, data); +} + +static u32 mt6363_read_field(u32 reg, u32 mask, u32 shift) +{ + assert(pmif_arb); + return pmif_arb->read_field(pmif_arb, SPMI_SLAVE_4, reg, mask, shift); +} + +void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + assert(pmif_arb); + pmif_arb->write_field(pmif_arb, SPMI_SLAVE_4, reg, val, mask, shift); +} + +static void pmic_set_power_hold(void) +{ + printk(BIOS_INFO, "[%s]before POWER_HOLD = 0x%x\n", __func__, + mt6363_read_field(PMIC_PWRHOLD, 0x1, 0)); + mt6363_write_field(PMIC_PWRHOLD, 0x1, 0x1, 0); + printk(BIOS_INFO, "[%s]POWER_HOLD = 0x%x\n", __func__, + mt6363_read_field(PMIC_PWRHOLD, 0x1, 0)); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + mt6363_write_field(PMIC_TOP_RST_MISC1_SET, 0x20, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + mt6363_write_field(PMIC_TOP_RST_MISC1_CLR, 0x02, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + mt6363_write_field(PMIC_TOP_RST_MISC1_SET, 0x01, 0xFFFF, 0); + /* Enable BUCK/LDO WDT VOSEL Debug */ + mt6363_write_field(PMIC_TOP_VRCTL_DBG_CON0, 0x1, 0x1, 0); + /* Clear WDT status */ + mt6363_write_field(PMIC_TOP_RST_MISC1_SET, 0x1, 0x1, 3); + udelay(50); + mt6363_write_field(PMIC_TOP_RST_MISC1_CLR, 0x1, 0x1, 3); + printk(BIOS_INFO, "[%s]WDTRSTB[0x%x]=0x%x\n", __func__, PMIC_TOP_RST_MISC1, + mt6363_read_field(PMIC_TOP_RST_MISC1, 0xFF, 0)); +} + +static void pmic_protect_key_setting(bool lock) +{ + const struct pmic_setting *entry; + + for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) { + entry = &key_protect_setting[i]; + mt6363_write16(entry->addr, lock ? 0 : entry->val); + } + printk(BIOS_INFO, "%s done\n", __func__); +} + +void mt6363_buck_set_voltage(u32 buck_id, u32 buck_uv) +{ + u32 vol_offset, vol_reg, vol, vol_step; + + switch (buck_id) { + case MT6363_VBUCK2: + vol_offset = 0; + vol_reg = PMIC_VRCTL_VOSEL_VBUCK2; + vol_step = 6250; + break; + default: + printk(BIOS_WARNING, "[%s] Unknown buck_id %u", __func__, buck_id); + return; + }; + + vol = (buck_uv - vol_offset) / vol_step; + mt6363_write_field(vol_reg, vol, 0xFF, 0); + udelay(MT6363_SET_DELAY_US); + printk(BIOS_INFO, "%s: %d, %d\n", __func__, buck_id, vol); +} + +u32 mt6363_buck_get_voltage(u32 buck_id) +{ + u32 vol_shift, vol_offset, vol_reg, vol, vol_step; + + switch (buck_id) { + case MT6363_VBUCK2: + vol_shift = 0; + vol_offset = 0; + vol_reg = PMIC_VBUCK2_DBG0; + vol_step = 6250; + break; + case MT6363_VBUCK4: + vol_shift = 0; + vol_offset = 0; + vol_reg = PMIC_VBUCK4_DBG0; + vol_step = 6250; + break; + default: + printk(BIOS_WARNING, "[%s] Unknown buck_id %u", __func__, buck_id); + return 0; + }; + + vol = mt6363_read_field(vol_reg, 0xFF, vol_shift); + printk(BIOS_INFO, "%s: %d, %d\n", __func__, buck_id, vol); + return vol_offset + vol * vol_step; +} + +void mt6363_set_vm18_voltage(u32 vm18_uv) +{ + u8 reg_vol; + + assert(pmif_arb); + assert(vm18_uv >= 1700000); + assert(vm18_uv < 2000000); + + reg_vol = ((vm18_uv - 1700000) / 50000) + 12; + mt6363_write8(PMIC_VM18_ANA_CON1, reg_vol); + mt6363_write8(PMIC_VM18_ANA_CON0, 0x0); + udelay(MT6363_SET_DELAY_US); + printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vm18_uv); +} + +u32 mt6363_get_vm18_voltage(void) +{ + u32 reg_vol, reg_cali, voltage; + + assert(pmif_arb); + + reg_cali = mt6363_read_field(PMIC_VM18_ANA_CON0, 0xF, 0); + reg_vol = mt6363_read_field(PMIC_VM18_ANA_CON1, 0xF, 0); + voltage = (reg_vol - 12) * 50000 + reg_cali * 5000 + 1700000; + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, %d\n", __func__, + reg_vol, reg_cali, voltage); + return voltage; +} + +void mt6363_set_vtref18_voltage(u32 vtref18_uv) +{ + u8 reg_vol, reg_cali; + + assert(pmif_arb); + assert(vtref18_uv >= 1800000); + assert(vtref18_uv <= 3400000); + + reg_cali = ((vtref18_uv - 1800000) % 100000) / 10000; + reg_vol = (vtref18_uv - 1800000) / 100000; + mt6363_write8(PMIC_VTREF18_ANA_CON0, reg_cali); + mt6363_write8(PMIC_VTREF18_ANA_CON1, reg_vol); + udelay(MT6363_SET_DELAY_US); + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, %d\n", __func__, reg_vol, reg_cali, + vtref18_uv); +} + +u32 mt6363_get_vtref18_voltage(void) +{ + u32 reg_vol, reg_cali, vtref18_uv; + + assert(pmif_arb); + + reg_cali = mt6363_read_field(PMIC_VTREF18_ANA_CON0, 0xF, 0); + reg_vol = mt6363_read_field(PMIC_VTREF18_ANA_CON1, 0xF, 0); + vtref18_uv = reg_cali * 10000 + reg_vol * 100000 + 1800000; + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, %d\n", __func__, reg_vol, reg_cali, + vtref18_uv); + return vtref18_uv; +} + +void mt6363_enable_vtref18(bool enable) +{ + mt6363_write_field(PMIC_LDO_VTREF18_CON0, enable, 0x1, 0); +} + +void mt6363_enable_buck5(bool enable) +{ + mt6363_write_field(PMIC_VBUCK5_OP_EN_2, enable, 0x7, 0); +} + +void mt6363_enable_vcn15(bool enable) +{ + mt6363_write_field(PMIC_LDO_VCN15_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf09(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF09_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf12(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF12_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf13(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF13_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf18(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF18_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vram_digrf(bool enable) +{ + mt6363_write_field(PMIC_LDO_VSRAM_DIGRF_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vram_mdfe(bool enable) +{ + mt6363_write_field(PMIC_LDO_VSRAM_MDFE_CON0, enable, 0x1, 0); +} + +void mt6363_init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1); + assert(pmif_arb); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spi"); + + printk(BIOS_INFO, "[%s][MT6363]CHIP ID = 0x%x\n", __func__, + mt6363_read_field(PMIC_SWCID1, 0xFF, 0)); +} + +void mt6363_init(void) +{ + mt6363_init_pmif_arb(); + pmic_set_power_hold(); + pmic_wdt_set(); + pmic_protect_key_setting(false); + pmic_init_setting(); + pmic_protect_key_setting(true); +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index f898775..7a950d2 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -30,6 +30,7 @@ romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c @@ -43,6 +44,7 @@ ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c +ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += soc.c ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c diff --git a/src/soc/mediatek/mt8196/mt6363.c b/src/soc/mediatek/mt8196/mt6363.c new file mode 100644 index 0000000..e41ce0e --- /dev/null +++ b/src/soc/mediatek/mt8196/mt6363.c @@ -0,0 +1,390 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6363TP_PMIC_Design_Notice_for_MT8196G_V0.2". + * The setting values are provided by MeidaTek designers. + */ + +#include <console/console.h> +#include <soc/mt6363.h> + +static const struct pmic_setting init_setting[] = { + {0x16, 0xA, 0xA}, + {0x19, 0x1F, 0x1F}, + {0x21, 0x1, 0x1}, + {0x22, 0x1, 0x1}, + {0x47, 0x0, 0xFF}, + {0x4A, 0x0, 0x80}, + {0x55, 0x5, 0x5}, + {0x8E, 0x60, 0xFF}, + {0x91, 0xC0, 0xFF}, + {0xAD, 0x0, 0x38}, + {0x10F, 0x10, 0x10}, + {0x112, 0x4, 0x4}, + {0x12D, 0x1, 0x1}, + {0x139, 0x21, 0x21}, + {0x230, 0x0, 0x1}, + {0x413, 0x7, 0xFF}, + {0x416, 0x12, 0xFF}, + {0x417, 0x0, 0x7}, + {0x90D, 0x10, 0x10}, + {0x98A, 0x10, 0x10}, + {0xA08, 0x1, 0x1}, + {0xA0C, 0x78, 0x7F}, + {0xA0E, 0x0, 0x2}, + {0xA0F, 0x1, 0x1}, + {0xA10, 0xE0, 0xE0}, + {0xA14, 0x40, 0x60}, + {0xA22, 0x80, 0x80}, + {0xA26, 0xFF, 0xFF}, + {0xA27, 0xFF, 0xFF}, + {0xA28, 0xFF, 0xFF}, + {0xA29, 0xFF, 0xFF}, + {0xA2A, 0x1, 0x1}, + {0xA39, 0x35, 0xFF}, + {0xA3A, 0x1, 0xFF}, + {0xA3B, 0x2, 0xFF}, + {0xA3C, 0x1C, 0xFF}, + {0xA3D, 0x20, 0xFF}, + {0xA3E, 0x34, 0xFF}, + {0xA3F, 0x34, 0xFF}, + {0xA40, 0x3, 0xFF}, + {0xA41, 0x1E, 0xFF}, + {0xA42, 0x1C, 0xFF}, + {0xA43, 0x2B, 0xFF}, + {0xA44, 0x1F, 0xFF}, + {0xA45, 0x1F, 0xFF}, + {0xA46, 0x2, 0xFF}, + {0xA47, 0x1F, 0xFF}, + {0xA48, 0x22, 0xFF}, + {0xA49, 0x22, 0xFF}, + {0xA4A, 0x22, 0xFF}, + {0xA4B, 0xFF, 0xFF}, + {0xA4C, 0x21, 0xFF}, + {0xA4D, 0x24, 0xFF}, + {0xA4E, 0x34, 0xFF}, + {0xA4F, 0x24, 0xFF}, + {0xA50, 0x30, 0xFF}, + {0xA51, 0x2A, 0xFF}, + {0xA52, 0x2B, 0xFF}, + {0xA53, 0x22, 0xFF}, + {0xA54, 0x23, 0xFF}, + {0xA55, 0xFF, 0xFF}, + {0xA56, 0x34, 0xFF}, + {0xA57, 0x5, 0xFF}, + {0xA58, 0x20, 0xFF}, + {0xA59, 0xFF, 0xFF}, + {0xA5A, 0xFF, 0xFF}, + {0xA5B, 0xFF, 0xFF}, + {0xC88, 0x10, 0x10}, + {0xC89, 0x18, 0xFE}, + {0xC8A, 0x4, 0xFF}, + {0xC90, 0x44, 0x7F}, + {0xD08, 0x0, 0x1}, + {0xDA1, 0x4, 0x7}, + {0xE88, 0x0, 0x40}, + {0xE89, 0x40, 0x40}, + {0xF8C, 0x15, 0x15}, + {0xF8D, 0x5, 0x5}, + {0x1188, 0x0, 0x80}, + {0x140E, 0x0, 0x40}, + {0x1445, 0x0, 0xFF}, + {0x1446, 0x0, 0xFF}, + {0x1447, 0x0, 0xF}, + {0x1487, 0x6C, 0xFF}, + {0x1488, 0x0, 0x1}, + {0x148A, 0x19, 0x7F}, + {0x148B, 0x33, 0x7F}, + {0x1507, 0x40, 0xFF}, + {0x1508, 0x0, 0x1}, + {0x150A, 0x5, 0x7F}, + {0x150B, 0x19, 0x7F}, + {0x1587, 0xA8, 0xFF}, + {0x1588, 0x0, 0x1}, + {0x158A, 0x5, 0x7F}, + {0x158B, 0x19, 0x7F}, + {0x1607, 0x40, 0xFF}, + {0x1608, 0x0, 0x1}, + {0x160A, 0x5, 0x7F}, + {0x160B, 0x19, 0x7F}, + {0x1687, 0x78, 0xFF}, + {0x1688, 0x0, 0x1}, + {0x168A, 0xC, 0x7F}, + {0x168B, 0x19, 0x7F}, + {0x1707, 0x40, 0xFF}, + {0x1708, 0x0, 0x1}, + {0x170A, 0xC, 0x7F}, + {0x1787, 0x40, 0xFF}, + {0x1788, 0x0, 0x1}, + {0x178A, 0x5, 0x7F}, + {0x1807, 0x40, 0xFF}, + {0x1808, 0x0, 0x1}, + {0x180A, 0x5, 0x7F}, + {0x1887, 0x98, 0xFF}, + {0x1888, 0x0, 0x1}, + {0x188A, 0x19, 0x7F}, + {0x188B, 0x33, 0x7F}, + {0x1907, 0xA0, 0xFF}, + {0x1908, 0x0, 0x1}, + {0x190A, 0xC, 0x7F}, + {0x190B, 0x19, 0x7F}, + {0x198A, 0x2E, 0x2F}, + {0x198C, 0xF8, 0xF8}, + {0x198D, 0x32, 0x3F}, + {0x198F, 0xC, 0xC}, + {0x1990, 0xED, 0xFF}, + {0x1991, 0x10, 0xFF}, + {0x1992, 0x0, 0xF}, + {0x1995, 0x60, 0x60}, + {0x1996, 0x45, 0xFF}, + {0x1997, 0x2, 0x2}, + {0x1998, 0x10, 0x10}, + {0x1999, 0x2D, 0x2F}, + {0x199B, 0xF8, 0xF8}, + {0x199C, 0x32, 0x3F}, + {0x199E, 0xC, 0xC}, + {0x199F, 0xED, 0xFF}, + {0x19A0, 0x0, 0xFF}, + {0x19A4, 0x60, 0x60}, + {0x19A5, 0x45, 0xFF}, + {0x19A6, 0x2, 0x2}, + {0x19AC, 0x85, 0x87}, + {0x19AF, 0x0, 0x1}, + {0x19B4, 0x3, 0x87}, + {0x19B7, 0x0, 0x1}, + {0x1A08, 0x10, 0x10}, + {0x1A09, 0x2D, 0x2F}, + {0x1A0B, 0xF8, 0xF8}, + {0x1A0C, 0x32, 0x3F}, + {0x1A0E, 0xC, 0xC}, + {0x1A0F, 0xED, 0xFF}, + {0x1A10, 0x0, 0xFF}, + {0x1A12, 0x10, 0x50}, + {0x1A13, 0x2D, 0x2F}, + {0x1A14, 0xC1, 0xC1}, + {0x1A15, 0xFA, 0xFF}, + {0x1A16, 0x32, 0x3F}, + {0x1A18, 0xC, 0xC}, + {0x1A19, 0x77, 0xFF}, + {0x1A1A, 0xC0, 0xFF}, + {0x1A1B, 0x2B, 0x7F}, + {0x1A1C, 0x10, 0x50}, + {0x1A1D, 0x2D, 0x2F}, + {0x1A1E, 0xC1, 0xC1}, + {0x1A1F, 0xFA, 0xFF}, + {0x1A20, 0x32, 0x3F}, + {0x1A22, 0xC, 0xC}, + {0x1A23, 0x77, 0xFF}, + {0x1A24, 0xC0, 0xFF}, + {0x1A25, 0x2B, 0x7F}, + {0x1A27, 0x2E, 0x2F}, + {0x1A29, 0xF8, 0xF8}, + {0x1A2A, 0x32, 0x3F}, + {0x1A2C, 0xC, 0xC}, + {0x1A2D, 0xED, 0xFF}, + {0x1A2E, 0x10, 0xFF}, + {0x1A2F, 0x0, 0xF}, + {0x1A36, 0x4, 0xC}, + {0x1A37, 0xFE, 0xFF}, + {0x1A39, 0xCD, 0xFF}, + {0x1A3A, 0x7F, 0xFF}, + {0x1A3B, 0x7F, 0xFF}, + {0x1A3C, 0x45, 0xFF}, + {0x1A3D, 0xF0, 0xF0}, + {0x1A45, 0x6, 0x87}, + {0x1A4C, 0x6, 0x87}, + {0x1A53, 0x6, 0x87}, + {0x1A5A, 0x5, 0x87}, + {0x1A5D, 0x0, 0x78}, + {0x1A88, 0x10, 0x50}, + {0x1A89, 0x2D, 0x2F}, + {0x1A8B, 0xF8, 0xF8}, + {0x1A8C, 0x32, 0x3F}, + {0x1A8E, 0xC, 0xC}, + {0x1A8F, 0xED, 0xFF}, + {0x1A90, 0x0, 0xFF}, + {0x1A92, 0x10, 0x50}, + {0x1A93, 0x2D, 0x2F}, + {0x1A94, 0x0, 0x1}, + {0x1A95, 0xFC, 0xFF}, + {0x1A96, 0x32, 0x3F}, + {0x1A98, 0xC, 0xC}, + {0x1A99, 0xED, 0xFF}, + {0x1A9A, 0x0, 0xFF}, + {0x1A9B, 0x0, 0xF}, + {0x1A9C, 0x10, 0x10}, + {0x1A9D, 0x2D, 0x2F}, + {0x1A9E, 0xC1, 0xC1}, + {0x1A9F, 0xFA, 0xFF}, + {0x1AA0, 0x32, 0x3F}, + {0x1AA2, 0xC, 0xC}, + {0x1AA3, 0x77, 0xFF}, + {0x1AA4, 0xC0, 0xFF}, + {0x1AA5, 0x2B, 0x7F}, + {0x1AA6, 0x10, 0x10}, + {0x1AA7, 0x2D, 0x2F}, + {0x1AA8, 0xC1, 0xC1}, + {0x1AA9, 0xFA, 0xFF}, + {0x1AAA, 0x32, 0x3F}, + {0x1AAC, 0xC, 0xC}, + {0x1AAD, 0x77, 0xFF}, + {0x1AAE, 0xC0, 0xFF}, + {0x1AAF, 0x2B, 0x7F}, + {0x1AB7, 0xFC, 0xFE}, + {0x1AB9, 0xCD, 0xFF}, + {0x1ABA, 0xCD, 0xFF}, + {0x1ABB, 0x7F, 0xFF}, + {0x1ABC, 0x7F, 0xFF}, + {0x1ABD, 0xF0, 0xF0}, + {0x1ABE, 0x0, 0x20}, + {0x1AC5, 0x6, 0x87}, + {0x1ACC, 0x6, 0x87}, + {0x1AD3, 0x6, 0x87}, + {0x1ADA, 0x6, 0x87}, + {0x1ADD, 0x10, 0x78}, + {0x1B0D, 0xF, 0xF}, + {0x1B0E, 0x1, 0x1}, + {0x1B11, 0xFF, 0xFF}, + {0x1B14, 0xFF, 0xFF}, + {0x1B17, 0xFF, 0xFF}, + {0x1B1A, 0x1, 0x1}, + {0x1B33, 0x8, 0x8}, + {0x1B88, 0x10, 0x10}, + {0x1B89, 0x0, 0x80}, + {0x1B96, 0x10, 0x10}, + {0x1B97, 0x0, 0x80}, + {0x1BA4, 0x10, 0x10}, + {0x1BA5, 0x0, 0x80}, + {0x1BB2, 0x10, 0x10}, + {0x1BB3, 0x0, 0x80}, + {0x1BC0, 0x10, 0x10}, + {0x1BC1, 0x0, 0x80}, + {0x1BCE, 0x10, 0x10}, + {0x1BCF, 0x0, 0x80}, + {0x1C08, 0x10, 0x10}, + {0x1C09, 0x0, 0x80}, + {0x1C0E, 0x40, 0x40}, + {0x1C16, 0x10, 0x10}, + {0x1C17, 0x0, 0x80}, + {0x1C1C, 0x40, 0x40}, + {0x1C24, 0x10, 0x10}, + {0x1C25, 0x0, 0x80}, + {0x1C32, 0x10, 0x10}, + {0x1C33, 0x0, 0x80}, + {0x1C40, 0x10, 0x10}, + {0x1C41, 0x0, 0x80}, + {0x1C4E, 0x10, 0x10}, + {0x1C4F, 0x0, 0x80}, + {0x1C88, 0x10, 0x10}, + {0x1C89, 0x0, 0x80}, + {0x1C96, 0x10, 0x10}, + {0x1C97, 0x0, 0x80}, + {0x1CA4, 0x10, 0x10}, + {0x1CA5, 0x0, 0x80}, + {0x1CB2, 0x10, 0x10}, + {0x1CB3, 0x0, 0x80}, + {0x1CC0, 0x10, 0x10}, + {0x1CC1, 0x0, 0x80}, + {0x1D08, 0x10, 0x10}, + {0x1D09, 0x0, 0x80}, + {0x1D1E, 0x10, 0x10}, + {0x1D1F, 0x0, 0x80}, + {0x1D23, 0x20, 0x7F}, + {0x1D27, 0xC, 0x7F}, + {0x1D28, 0x19, 0x7F}, + {0x1D88, 0x10, 0x10}, + {0x1D89, 0x0, 0x80}, + {0x1D8D, 0x18, 0x7F}, + {0x1D91, 0x5, 0x7F}, + {0x1D92, 0x19, 0x7F}, + {0x1DA3, 0x10, 0x10}, + {0x1DA4, 0x0, 0x80}, + {0x1DA8, 0x4C, 0x7F}, + {0x1DAC, 0x5, 0x7F}, + {0x1DAD, 0x19, 0x7F}, + {0x1DB8, 0x14, 0x1C}, + {0x1DB9, 0xF, 0xF}, + {0x1DBA, 0xC0, 0xFF}, + {0x1DBC, 0x60, 0xFF}, + {0x1E08, 0x10, 0x10}, + {0x1E09, 0x0, 0x80}, + {0x1E0D, 0x7F, 0x7F}, + {0x1E11, 0xF, 0x7F}, + {0x1E12, 0x14, 0x7F}, + {0x1E1E, 0x10, 0x10}, + {0x1E1F, 0x0, 0x80}, + {0x1E27, 0xF, 0x7F}, + {0x1E28, 0x14, 0x7F}, + {0x1E88, 0x10, 0x10}, + {0x1E89, 0x0, 0x80}, + {0x1E8D, 0x7F, 0x7F}, + {0x1E91, 0x5, 0x7F}, + {0x1E92, 0x19, 0x7F}, + {0x1E9E, 0x10, 0x10}, + {0x1E9F, 0x0, 0x80}, + {0x1EA3, 0x58, 0x7F}, + {0x1EA7, 0xC, 0x7F}, + {0x1EA8, 0xC, 0x7F}, + {0x1F16, 0x2, 0x3}, + {0x1F17, 0x0, 0xF}, + {0x1F1B, 0x2, 0xF}, + {0x1F1E, 0x2, 0x3}, + {0x1F2A, 0x2, 0x3}, + {0x1F2E, 0x2, 0x3}, + {0x1F8A, 0x8, 0xC}, + {0x1F8C, 0x4, 0x6}, + {0x1F8E, 0x4, 0x6}, + {0x1F90, 0x4, 0x6}, + {0x1F94, 0x2, 0x3}, + {0x1F98, 0x1, 0x3}, + {0x1F9C, 0x1, 0x3}, + {0x1FA0, 0x2, 0x3}, + {0x1FA4, 0x8, 0xC}, + {0x1FAB, 0x8, 0xC}, + {0x1FAD, 0x4, 0x6}, + {0x1FB0, 0x0, 0x10}, + {0x2207, 0xE0, 0xE0}, + {0x2208, 0xE0, 0xE0}, + {0x2209, 0xE0, 0xE0}, + {0x220A, 0xE0, 0xE0}, + {0x2214, 0xF0, 0xF0}, + {0x2216, 0x0, 0x7}, + + /* Add UVLO 2.0 setting. also need to modify dts setting for main pmic */ + {0xA5E, 0x2, 0x2}, + {0xA89, 0x4, 0xF}, + {0xA8A, 0x4, 0xF}, + {0xA95, 0x40, 0x40}, + /* + * 1. Set VS1_VOTER_VOSEL = 1.8875V + * 2. Set VS1_VOTER_EN = 0x8 (bit3 for VS1 users) + */ + {0x18A0, 0x97, 0xFF}, + {0x189A, 0x8, 0xFF}, + /* + * 1. Set VS2_VOTER_VOSEL = 1.275V + * 2. Set VS2_VOTER_EN = 0x48 (bit6/3 for VS2 users) + */ + {0x14A0, 0x66, 0xFF}, + {0x149A, 0x48, 0xFF}, + /* + * 1. Set VS3_VOTER_VOSEL = 0.975V + * 2. Set VS3_VOTER_EN = 0x8 (bit3 for VS3 users) + */ + {0x1920, 0x9C, 0xFF}, + {0x191A, 0x8, 0xFF}, +}; + +void pmic_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting); i++) + mt6363_write_field(init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, 0); + + /* + * TODO: Disable unused modem power in a separate function and + * call that function from mainboard folder. + */ + printk(BIOS_INFO, "%s done\n", __func__); +}