[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake

[Saurabh Mishra (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Subrata Banik, Wonkyu Kim.

Saurabh Mishra has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )

Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
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Patch Set 72:

(5 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83772/comment/99cc437c_2172f17d?usp... :
PS66, Line 12: wake up
> waking up or wakeup or wake-up

wake-up

https://review.coreboot.org/c/coreboot/+/83772/comment/199d2ca9_061895f4?usp... :
PS66, Line 14: ,
> Not needed.

Acknowledged

https://review.coreboot.org/c/coreboot/+/83772/comment/cd00d226_7cc7acc0?usp... :
PS66, Line 15:   common/block/acpi/acpi/northbridge.asl binding with PTL change,
             :   #if DMI_BASE_SIZE gaurd check is added in northbridge.asl
> Indent with one more space to align with above. […]

Acknowledged

https://review.coreboot.org/c/coreboot/+/83772/comment/d371a0c4_12e19965?usp... :
PS66, Line 16: gaurd
> guard

Acknowledged

File src/soc/intel/pantherlake/acpi/tcss.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/d616ad38_1e38293e?usp... :
PS66, Line 7: Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI),
            :  * USB device controller(xDCI)
> Please add a space before (.

Acknowledged