[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/var/felwinter: Correct SSD power sequence

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58044 )

Change subject: mb/google/brya/var/felwinter: Correct SSD power sequence
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mb/google/brya/var/felwinter: Correct SSD power sequence

M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5

Signed-off-by: Eric Lai 
Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/felwinter/gpio.c
1 file changed, 15 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c
index f7ad2ef..62610ac 100644
--- a/src/mainboard/google/brya/variants/felwinter/gpio.c
+++ b/src/mainboard/google/brya/variants/felwinter/gpio.c
@@ -113,10 +113,14 @@
 static const struct pad_config early_gpio_table[] = {
    /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
    /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
    PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
    /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
    PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
    /* D18 : UART1_TXD ==> SD_PE_RST_L */
    PAD_CFG_GPO(GPP_D18, 0, PLTRST),
    /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
@@ -131,6 +135,11 @@
    PAD_CFG_GPO(GPP_H13, 1, PLTRST),
 };

+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
 const struct pad_config *variant_gpio_override_table(size_t *num)
 {
    *num = ARRAY_SIZE(override_gpio_table);
@@ -142,3 +151,9 @@
    *num = ARRAY_SIZE(early_gpio_table);
    return early_gpio_table;
 }
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.