Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31950
Change subject: device/pciexp_device: Add set_subsystem() for pciexp device ......................................................................
device/pciexp_device: Add set_subsystem() for pciexp device
This patch performs below operations
1. Add new function to perform subsystem programming for PCIE devices.
2. Remove duplicate implementaion of PCIE subsystem programming and refer the same from common pciexp_device.c.
Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/device/pciexp_device.c M src/include/device/pciexp.h M src/northbridge/intel/sandybridge/pcie.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/lynxpoint/pcie.c 10 files changed, 23 insertions(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31950/1
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c209816..318f8cd 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -463,9 +463,16 @@ pciexp_enable_ltr(dev); }
+void pciexp_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + /** Default device operations for PCI Express bridges */ static struct pci_operations pciexp_bus_ops_pci = { - .set_subsystem = 0, + .set_subsystem = pciexp_set_subsystem, };
struct device_operations default_pciexp_ops_bus = { diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 0f1420a..121b998 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -2,6 +2,9 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */
+/* PCI-E Sub-System ID */ +#define PCIE_SUBSYSTEM_VENDOR_ID 0x94 + enum aspm_type { PCIE_ASPM_NONE = 0, PCIE_ASPM_L0S = 1, @@ -22,4 +25,8 @@ extern struct device_operations default_pciexp_ops_bus;
unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap); + +void pciexp_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); + #endif /* DEVICE_PCIEXP_H */ diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 16bc314..6ffe2d3 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -65,20 +65,8 @@ } #endif
-static void -pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!ven || !device) - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (ven & 0xffff)); -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 32135ee..fdb8782 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -649,16 +649,6 @@ root_port_commit_config(); }
-static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) - pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, (device << 16) | vendor); -} - static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ @@ -666,7 +656,7 @@ }
static struct pci_operations pcie_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, .set_L1_ss_latency = pcie_set_L1_ss_max_latency, };
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 0a5e1bf..1c3114b 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -25,8 +25,6 @@ #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 -/* PCI-E Sub-System ID */ -#define PCIE_SUBSYSTEM_VENDOR_ID 0x94
static void pch_pcie_init(struct device *dev) { @@ -72,16 +70,9 @@ PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); }
-static void pcie_dev_set_subsystem(struct device *dev, - unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, - .set_subsystem = pcie_dev_set_subsystem, + .set_subsystem = pciexp_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 39c53e8..3e2d5fb 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -306,21 +306,8 @@ return NULL; }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 4679ee5..c412927 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -252,22 +252,8 @@ root_port_commit_config(dev); }
- -static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a36fdc6..fee77ee 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -95,19 +95,6 @@ } }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801ix_config *config = dev->chip_info; @@ -121,7 +108,7 @@ }
static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index fb90cd9..1f0038f 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -95,19 +95,6 @@ } }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801jx_config *config = dev->chip_info; @@ -121,7 +108,7 @@ }
static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 695abf2..9479a37 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -727,21 +727,8 @@ root_port_commit_config(); }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, };
static struct device_operations device_ops = {