Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56915 )
Change subject: mb/google/brya: set PL4 value dynamically for thermal ......................................................................
mb/google/brya: set PL4 value dynamically for thermal
Set PL4 value dynamically for brya board based on CPU SKUs which is detectable at runtime.
BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000)
Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 2 files changed, 10 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/56915/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index 35cb488..f7a97f3 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -7,6 +7,7 @@ #include <soc/pci_devs.h>
#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h>
void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { @@ -25,6 +26,10 @@
struct drivers_intel_dptf_config *config = policy_dev->chip_info;
+ struct soc_power_limits_config *soc_config; + config_t *conf = config_of_soc(); + soc_config = conf->power_limits_config; + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
for (size_t i = 0; i < num_entries; i++) { @@ -34,11 +39,13 @@ settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; - printk(BIOS_INFO, "Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u)\n", + soc_config->tdp_pl4 = limits[i].pl4_power; + printk(BIOS_INFO, "Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, limits[i].pl1_max_power, limits[i].pl2_min_power, - limits[i].pl2_max_power); + limits[i].pl2_max_power, + limits[i].pl4_power); } } } diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index b992129..62d8094 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -31,6 +31,7 @@ unsigned int pl1_max_power; unsigned int pl2_min_power; unsigned int pl2_max_power; + unsigned int pl4_power; };
/* Modify Power Limit devictree settings during ramstage */