[coreboot-gerrit] Patch set updated for coreboot: smscsuperio: map interrupt in smscsuperio_enable_serial()

[Jonathan A. Kollasch]

Jonathan A. Kollasch ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10807

-gerrit

commit 612927b6bdc51b3c1e1ccd90b45587afb088a806
Author: Jonathan A. Kollasch 
Date:   Mon Jul 6 08:07:50 2015 -0500

smscsuperio: map interrupt in smscsuperio_enable_serial()

This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the
    interrupt is unmapped at reset, but for whatever reason the chip is
    inaccessible in smscsuperio/superio.c::enable_dev() and thus the
    devicetree.cb IRQ information is not applied in ramstage and then
    serial console output fails to work for more than the UART FIFO depth
    in the OS.

Change-Id: I00998088975569516f7caeb7f4098b48fe437889
    Signed-off-by: Jonathan A. Kollasch 
---
 src/superio/smsc/smscsuperio/early_serial.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c
index 3eb9347..0d5d6d0 100644
--- a/src/superio/smsc/smscsuperio/early_serial.c
+++ b/src/superio/smsc/smscsuperio/early_serial.c
@@ -55,6 +55,14 @@ void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase)
    pnp_set_logical_device(dev);
    pnp_set_enable(dev, 0);
    pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	switch (iobase) {
+	case 0x03f8:
+		pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
+		break;
+	case 0x02f8:
+		pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
+		break;
+	}
    pnp_set_enable(dev, 1);
    pnp_exit_conf_state(dev);
 }