Attention is currently required from: Kevin Chiu, Paul Menzel, Nick Vaccaro, Wisley Chen, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59305 )
Change subject: mb/google/brya/var/vell: update gpio override ......................................................................
Patch Set 13:
(6 comments)
File src/mainboard/google/brya/variants/vell/gpio.c:
https://review.coreboot.org/c/coreboot/+/59305/comment/2447d32d_df84d81b PS13, Line 54: /* H12 : I2C7_SDA ==> UWB_SDA */ : PAD_CFG_GPI_APIC(GPP_H12, NONE, PLTRST, LEVEL, NONE), : /* H13 : I2C7_SCL ==> UWB_SCL */ : PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST, LEVEL, NONE), This looks like an I2C bus, should these be configured as NF1 instead?
https://review.coreboot.org/c/coreboot/+/59305/comment/f9afb704_61ed1e20 PS13, Line 59: NF1 `NF6`
https://review.coreboot.org/c/coreboot/+/59305/comment/27711c1a_a2638bde PS13, Line 61: NF1 `NF6`
https://review.coreboot.org/c/coreboot/+/59305/comment/5127b8a2_a80fefdc PS13, Line 94: /*For DB2*/ : /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ : //PAD_CFG_NF(GPP_H6, NONE, DEEP, NF2), : /* H7 : I2C1_SDL ==> PCH_I2C_TPM_SCL */ : //PAD_CFG_NF(GPP_H7, NONE, DEEP, NF2), : /* B7 : ISH_12C1_SDA ==> PCH_I2C_TCHSCR_SDA */ : //PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), : /* B8 : ISH_12C1_SCL ==> PCH_I2C_TCHSCR_SCL */ : //PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), If these depend on FW_CONFIG, then you will have to program them separately (see anahera/fw_config.c for an example)
https://review.coreboot.org/c/coreboot/+/59305/comment/b20e8fd0_0c2f014f PS13, Line 109: /* B4 : PROC_GP3 ==> SSD_PERST_L */ : PAD_CFG_GPO(GPP_B4, 0, DEEP), This is a duplicate, B4 is programmed near the end of this table (this is what we want)
https://review.coreboot.org/c/coreboot/+/59305/comment/0e963fbb_ac5f899b PS13, Line 150: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), reset type for all of these needs to be `PLTRST`