Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40488 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
XMP memory profiles support which has been tested on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 245 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/40488/1
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3e3a0e9..7f85852 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -42,6 +42,10 @@
endchoice
+if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + if CPU_AMD_AGESA_BINARY_PI source "src/vendorcode/amd/pi/Kconfig" endif diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..817c4b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,43 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if CPU_AMD_AGESA_FAMILY14 || CPU_AMD_AGESA_FAMILY15_TN || CPU_AMD_AGESA_FAMILY16_KB + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, i.e. XMP 1. + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist on ANY of your RAM sticks! If in doubt, + check their SPD Data using a coreboot's great fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! + +endchoice + +endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index 3b37429..c7f490d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@
#define SPD_FTB 9
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -103,18 +105,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index ab46e4a..bbe5c12 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,6 +94,8 @@
#define SPD_FTB 9
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -102,18 +104,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f..bc608a5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@
#define SPD_FTB 9
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -103,18 +105,82 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +188,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38
-#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *-----------------------------