Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31445 )
Change subject: soc/intel/cannonlake: Add a power control workaround for SD controller ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/#/c/31445/8/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig:
https://review.coreboot.org/#/c/31445/8/src/soc/intel/cannonlake/Kconfig@238 PS8, Line 238: config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
This adds a redundant setting. If I'm not complete confused, […]
The Active High/Low is configurable, and is a SoC setting that can be provided to FSP silicon init. i.e., SdCardPowerEnableActiveHigh. I assume that this setting cannot be accessed in the ASL code. Hence the need for config.
https://review.coreboot.org/#/c/31445/2/src/soc/intel/cannonlake/acpi/scs.as... File src/soc/intel/cannonlake/acpi/scs.asl:
https://review.coreboot.org/#/c/31445/2/src/soc/intel/cannonlake/acpi/scs.as... PS2, Line 134: CTXS(SD_PWR_EN_PIN)
That's neither what I meant nor how CTXS does it. It does preserve […]
ok I get, was leaving it upto chance (earlier programming) for now :). I will create another function to update the TX buffer enable/disable.